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MAX5879
  • MAX5879

MAX5879

PRODUCTION

14-Bit, 2.3Gsps Direct RF Synthesis DAC with Selectable Frequency Response Synthesize High-Quality Wideband Signals from DC to Greater Than 2GHz

Analog Devices MAX5879 Product Info

10 February 2026 6

Features

  • Industry-Leading Performance
    • WCDMA ACLR: 70dB at 2.14GHz
    • DOCSIS ACP: -70dBc at 400MHz, 8 Channel (256 QAM)
    • Noise Density: -165dBc/Hz at 200MHz
  • High Output Power: 9dBm (CW)
  • Frequency-Response Modes: NRZ, RZ, RF, RFZ
  • 2GHz Output Bandwidth
  • 2:1 or 4:1 Multiplexed LVDS Inputs
    • Up to 1150MHz Each Port
    • Single or Double Data-Rate Operation
  • On-Chip DLL for Input Data Synchronization
  • Reset Function for Multiple DAC Synchronization

Part details & applications

The MAX5879 is a high-performance, 14-bit, 2.3Gsps digital-to-analog converter (DAC) capable of synthesizing high-frequency and wideband signals in baseband and higher-order Nyquist zones. The 2.3Gsps update rate, combined with the selectable frequency-response modes (NRZ, RZ, RF, and RFZ), allows digital generation of signals to more than 2GHz output frequency. The unique RFZ mode allows generation up to the 6th Nyquist zone, with update rates to 1150Msps. The device features excellent spurious, noise, and intermodulation distortion performance, and can directly synthesize signal bandwidths to more than 1GHz.

The device has four 14-bit, multiplexed, low-voltage differential signaling (LVDS) input ports that each operates up to 1150Mwps. The DAC operates with a clock rate (fCLK) up to 2.3GHz. The device has a selectable 2:1 or 4:1 input multiplexer that allows the user to select two data ports up to 1150Mwps each, or four data ports up to 575Mwps each. In turn, the input data rate is 1/2 or 1/4 the DAC update rate at each port. The device features a delay-locked loop (DLL) to ease data synchronization with FPGAs or ASICs. The parity input and parity error flag output can be used to detect bit errors between the data source and the DAC. The device also features a data clock reset circuit for aligning the data-capture clocks of multiple DACs.

The device has four selectable frequency-response output modes:

  1. Nonreturn-to-zero (NRZ) mode provides the highest dynamic range/output power in the 1st Nyquist zone.
  2. Return-to-zero (RZ) mode trades off SNR for improved gain flatness in the 1st, 2nd, and 3rd Nyquist zones.
  3. Radio-frequency (RF) mode provides higher SNR and excellent dynamic performance in the 2nd and 3rd Nyquist zones.
  4. Radio-frequency-return-to-zero (RFZ) mode provides high dynamic range and improved gain

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