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AD9627
  • AD9627
  • AD9627

AD9627

PRODUCTION

12-Bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter

Analog Devices AD9627 Product Info

10 February 2026 7

Features

  • SNR = 69.4 dBc (70.4 dBFS) to 70 MHz @
    125 MSPS
  • SFDR = 85 dBc to 70 MHz @ 125 MSPS
  • Low power: 750 mW @ 125 MSPS
  • SNR = 69.2 dBc (70.2 dBFS) to 70 MHz @
    150 MSPS
  • SFDR = 84 dBc to 70 MHz @ 150 MSPS
  • Low power: 820 mW @ 150 MSPS
  • 1.8 V analog supply operation
  • 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS output supply
  • Integer 1-to-8 input clock divider
  • IF sampling frequencies to 450 MHz
  • Internal ADC voltage reference
  • Integrated ADC sample-and-hold inputs
  • Please see Data Sheet for Additional Features

Part details & applications

The AD9627 is a dual, 12-bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS analog-to-digital converter (ADC). The AD9627 is designed to support communications applications where low cost, small size and versatility are desired.

The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

The AD9627 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The fast detect feature allows fast overrange detection by outputting four bits of input level information with very short latency.

In addition, the programmable threshold detector allows monitoring of the incoming signal power, using the four fast detect bits of the ADC with very low latency. If the input signal level exceeds the programmable threshold, the coarse upper threshold indicator goes high. Because this threshold indicator has very low latency, the user can quickly turn down the system gain to avoid an overrange condition.

The second AGC-related function is the signal monitor. This block allows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system.

The ADC output data can be routed directly to the two external 12-bit output ports. These outputs can be set from 1.8 V to 3.3 V CMOS or 1.8 V LVDS. Flexible power-down options allow significant power savings, when desired.

Programming for setup and control is accomplishe

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