AD9207

RECOMMENDED FOR NEW DESIGNS

12-Bit, 6 GSPS, JESD204B/JESD204C Dual ADC

Analog Devices AD9207 Product Info

10 February 2026 3

Features

Flexible reconfigurable common platform design
- Supports single, dual, and quad band per channel
- Datapaths and DSP blocks are fully bypassable
- On-chip PLL with multichip synchronization
- External RFCLK input option for off-chip PLL
Support clock input frequencies up to 12 GHz
- Maximum ADC sample rate up to 6 GSPS
- Useable analog bandwidth to 8 GHz
Maximum data rate up to 6 GSPS using JESD204C
Noise density: −153 dBFS/Hz
ADC AC performance at 6 GSPS, input at 2.7 GHz, −1 dBFS
- Full-scale sine wave input voltage: 1.475 V p-p
- Noise figure: 25.3 dB
- HD2: −70 dBFS
- HD3: −68 dBFS
- Worst other (excluding HD2 and HD3): −84 dBFS
Versatile digital features
- Selectable decimation filters
- Configurable DDC
  - 8 fine complex DDCs and 4 coarse complex DDCs
  - 48-bit NCO per DDC
  - Option to bypass fine and coarse DDC
- Programmable 192-tap PFIR filter for receive equalization

Supports 4 different profile settings loaded via the GPIOx pins
Programmable delay per datapath
- Receive AGC support
  - Fast detect with low latency for fast AGC control
- Signal monitor for slow AGC control
- Dedicated AGC support pins
Auxiliary features
- Fast frequency hopping
- ADC clock driver with selectable divide

Part details & applications

The AD9207 is a dual, 12-bit, 6 GSPS analog-to-digital converter (ADC). The ADC input features an on-chip wideband buffer with overload protection. This device is designed to support applications capable of direct sampling wideband signals up to 8 GHz. An onchip, low phase noise, phase-locked loop (PLL) clock synthesizer is available to generate the ADC sampling clock, which simplifies the printed circuit board (PCB) distribution of a high frequency clock signal. A clock output buffer is available to transmit the ADC sampling clock to other devices.

The dual ADC cores have code error rates (CER) better than 2 × 10⁻¹⁵. Low latency fast detection and signal monitoring are available for automatic gain control (AGC) purposes. A flexible 192-tap programmable finite impulse response filter (PFIR) is available for digital filtering and/or equalization. Programmable integer and fractional delay blocks support compensation for analog delay mismatches.

The digital signal processing (DSP) block consists of two coarse digital downconverters (DDCs) and four fine DDCs per ADC pair. Each ADC can operate with one or two main DDC stages in support of multiband applications. The four additional fine DDC stages are available to support up to four bands per ADC. The 48-bit numerically controlled oscillators (NCOs) associated with each DDC support fast frequency hopping (FFH) while maintaining synchronization with up to 16 unique frequency assignments selected via the general-purpose input and output (GPIOx) pins or the serial port interface (SPI).

The AD9207 supports one or two JTx links that can be configured for either JESD204B or JESD204C subclass operation, which allows different datapath configurations for each ADC. Multidevice synchronization is supported through the SYSREF± input pins.

See the Outline Dimensions section and the Ordering Guide section of the data sheet for more information.

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