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SN74LVC2G101
  • SN74LVC2G101
  • SN74LVC2G101
  • SN74LVC2G101
  • SN74LVC2G101

SN74LVC2G101

ACTIVE

Two-channel 1.1V-to-3.6V configurable gate for clock input with Schmitt-trigger inputs

Texas Instruments SN74LVC2G101 Product Info

1 April 2026 0

Parameters

Technology family

LVC

Supply voltage (min) (V)

1.1

Supply voltage (max) (V)

3.6

Number of channels

2

Inputs per channel

1

IOL (max) (mA)

24

IOH (max) (mA)

-24

Input type

Schmitt-Trigger

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Partial power down (Ioff)

Data rate (max) (Mbps)

100

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Package

TSSOP (PW)-16-32 mm² 5 x 6.4

Features

  • Operating range from 1.1V to 3.6V
  • Over-voltage tolerant inputs support up to 5.5V independent of VCC
  • Supports partial-power-down with back drive protection (Ioff)
  • High push-pull output drive strength:

    • ±24mA at 3.3V
    • ±8mA at 2.3V
    • ±4mA at 1.65V
  • Maximum propagation delay of 7ns at 3.3V supply
  • Latch-up performance exceeds 100mAper JESD78
  • Operating range from 1.1V to 3.6V
  • Over-voltage tolerant inputs support up to 5.5V independent of VCC
  • Supports partial-power-down with back drive protection (Ioff)
  • High push-pull output drive strength:

    • ±24mA at 3.3V
    • ±8mA at 2.3V
    • ±4mA at 1.65V
  • Maximum propagation delay of 7ns at 3.3V supply
  • Latch-up performance exceeds 100mAper JESD78

Description

The SN74LVC2G101 contains two independent D-type flip-flops. Each channel has data (D), clear (CLR), and clock (CLKA, CLKB, CLKC, CLKD) inputs and a non-inverted output (Q). The clock inputs can be configured for use in a wide variety of applications, allowing for configuration as 2-input AND, OR, NAND, NOR, XOR, XNOR, as well as 1-input inverted or non-inverted operation. All inputs include Schmitt-trigger architecture.

The SN74LVC2G101 contains two independent D-type flip-flops. Each channel has data (D), clear (CLR), and clock (CLKA, CLKB, CLKC, CLKD) inputs and a non-inverted output (Q). The clock inputs can be configured for use in a wide variety of applications, allowing for configuration as 2-input AND, OR, NAND, NOR, XOR, XNOR, as well as 1-input inverted or non-inverted operation. All inputs include Schmitt-trigger architecture.

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