Texas Instruments SN74LVC2G00 Product Info

Parameters

Technology family	LVC
Supply voltage (min) (V)	1.65
Supply voltage (max) (V)	5.5
Number of channels	2
Inputs per channel	2
IOL (max) (mA)	32
IOH (max) (mA)	-32
Input type	Standard CMOS
Output type	Push-Pull
Features	Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)
Data rate (max) (Mbps)	100
Rating	Catalog
Operating temperature range (°C)	-40 to 125

Package

DSBGA (YZP)-8-2.8125 mm² 2.25 x 1.25

Features

Available in the Texas Instruments
NanoFree™ Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 4.3 ns at 3.3 V
Low Power Consumption, 10-µA Max I_CC
±24-mA Output Drive at 3.3 V
Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A =
25°C
Typical V_OHV (Output V_OH Undershoot)
> 2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Live Insertion, Partial Power
Down Mode, and Back Drive Protection
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model
- 1000-V Charged-Device Model

Available in the Texas Instruments
NanoFree™ Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 4.3 ns at 3.3 V
Low Power Consumption, 10-µA Max I_CC
±24-mA Output Drive at 3.3 V
Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A =
25°C
Typical V_OHV (Output V_OH Undershoot)
> 2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Live Insertion, Partial Power
Down Mode, and Back Drive Protection
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model
- 1000-V Charged-Device Model

Description

This dual 2-input positive-NAND gate is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC2G00 device performs the Boolean function Y = A × B or Y = A + B in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This dual 2-input positive-NAND gate is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC2G00 device performs the Boolean function Y = A × B or Y = A + B in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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All In One Distributor

SN74LVC2G00

2-ch, 2-input, 1.65-V to 5.5-V NAND gates

Texas Instruments SN74LVC2G00 Product Info

Parameters

Package

Features

Description

SUBMITTED SUCCESSFULLY！

ELECTRONIC COMPONENTS All In One Distributor

SN74LVC2G00

2-ch, 2-input, 1.65-V to 5.5-V NAND gates

Texas Instruments SN74LVC2G00 Product Info

Parameters

Package

Features

Description

SUBMITTED SUCCESSFULLY！

ELECTRONIC COMPONENTS
All In One Distributor