0
Technology family |
LVC |
Supply voltage (min) (V) |
1.65 |
Supply voltage (max) (V) |
5.5 |
Number of channels |
1 |
Inputs per channel |
3 |
IOL (max) (mA) |
32 |
IOH (max) (mA) |
-32 |
Input type |
Standard CMOS |
Output type |
Push-Pull |
Features |
Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) |
Data rate (max) (Mbps) |
100 |
Rating |
Catalog |
Operating temperature range (°C) |
-40 to 125 |
DSBGA (YZP)-6-2.1875 mm² 1.75 x 1.25
This device is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G0832 device is a single 3-input positive AND-OR gate. It performs the Boolean function Y = (A • B ) + C in positive logic.
By tying one input to GND or VCC, the SN74LVC1G0832 device offers two more functions. When C is tied to GND, this device performs as a 2−input AND gate (Y = A • B). When A is tied to VCC, the device works as a 2−input OR gate (Y = B + C). This device also works as a 2−input OR gate when B is tied to VCC (Y = A + C).
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.