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SN74LVC166A
  • SN74LVC166A
  • SN74LVC166A
  • SN74LVC166A
  • SN74LVC166A

SN74LVC166A

ACTIVE

1.1V to 3.6V 8-bit parallel-load shift registers

Texas Instruments SN74LVC166A Product Info

1 April 2026 1

Parameters

Technology family

LVC

Supply voltage (min) (V)

1.1

Supply voltage (max) (V)

3.6

Input type

CMOS

Output type

Push-Pull

IOL (max) (mA)

24

IOH (max) (mA)

-24

Features

Over-voltage tolerant inputs, Partial power down (Ioff)

Operating temperature range (°C)

-40 to 125

Rating

Catalog

Package

SOIC (D)-16-59.4 mm² 9.9 x 6

Features

  • Operating range from 1.1V to 3.6V
  • Over-voltage tolerant inputs support up to 5.5V independent of VCC
  • Supports partial-power-down with back drive protection (Ioff)
  • High push-pull output drive strength:

    • ±24mA at 3.3V
    • ±8mA at 2.3V
    • ±4mA at 1.65V
  • Maximum propagation delay of 11.2ns at 3.3V supply
  • Latch-up performance exceeds 100mAper JESD78
  • Operating range from 1.1V to 3.6V
  • Over-voltage tolerant inputs support up to 5.5V independent of VCC
  • Supports partial-power-down with back drive protection (Ioff)
  • High push-pull output drive strength:

    • ±24mA at 3.3V
    • ±8mA at 2.3V
    • ±4mA at 1.65V
  • Maximum propagation delay of 11.2ns at 3.3V supply
  • Latch-up performance exceeds 100mAper JESD78

Description

The SN74LVC166A contains one 8-bit parallel-load shift register. Data is loaded synchronously using the shift or load (SH/LD) select and clock (CLK) inputs. The device includes a serial (SER) input to allow for daisy chaining and an asynchronous clear (CLR) input.

The SN74LVC166A contains one 8-bit parallel-load shift register. Data is loaded synchronously using the shift or load (SH/LD) select and clock (CLK) inputs. The device includes a serial (SER) input to allow for daisy chaining and an asynchronous clear (CLR) input.

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