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SN74LV8T165
  • SN74LV8T165
  • SN74LV8T165
  • SN74LV8T165
  • SN74LV8T165

SN74LV8T165

ACTIVE

1.65-V to 5.5-V 8-bit parallel-load shift register with voltage translation

Texas Instruments SN74LV8T165 Product Info

1 April 2026 5

Parameters

Technology family

LV1T

Vout (min) (V)

1.65

Vout (max) (V)

5.5

Data rate (max) (Mbps)

100

IOH (max) (mA)

-8

IOL (max) (mA)

8

Supply current (max) (µA)

2

Features

Balanced outputs, Single supply, Voltage translation

Input type

TTL-Compatible CMOS

Output type

Balanced CMOS

Operating temperature range (°C)

-40 to 125

Package

TSSOP (PW)-16-32 mm² 5 x 6.4

Features

  • Wide operating range of 1.8 V to 5.5 V

  • Single-supply voltage translator (refer to ):

    • Up translation:

      • 1.2 V to 1.8 V

      • 1.5 V to 2.5 V

      • 1.8 V to 3.3 V

      • 3.3 V to 5.0 V

    • Down translation:

      • 5.0 V, 3.3 V, 2.5 V to 1.8 V
      • 5.0 V, 3.3 V to 2.5 V
      • 5.0 V to 3.3 V
  • 5.5 V tolerant input pins
  • Supports standard pinouts
  • Up to 150Mbps with 5 V or 3.3 V V CC
  • Latching logic with known power-up state
  • Latch-up performance exceeds 250 mA per JESD 17
  • Wide operating range of 1.8 V to 5.5 V

  • Single-supply voltage translator (refer to ):

    • Up translation:

      • 1.2 V to 1.8 V

      • 1.5 V to 2.5 V

      • 1.8 V to 3.3 V

      • 3.3 V to 5.0 V

    • Down translation:

      • 5.0 V, 3.3 V, 2.5 V to 1.8 V
      • 5.0 V, 3.3 V to 2.5 V
      • 5.0 V to 3.3 V
  • 5.5 V tolerant input pins
  • Supports standard pinouts
  • Up to 150Mbps with 5 V or 3.3 V V CC
  • Latching logic with known power-up state
  • Latch-up performance exceeds 250 mA per JESD 17

Description

The SN74LV8T165 device is a parallel- or serial-in, serial-out 8-bit shift register. This device has two modes of operation: load data, and shift data which are controlled by the SH/ LD input. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example 3.3 V to 2.5 V output).

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