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SN74LV244A
  • SN74LV244A
  • SN74LV244A
  • SN74LV244A
  • SN74LV244A
  • SN74LV244A
  • SN74LV244A
  • SN74LV244A
  • SN74LV244A
  • SN74LV244A
  • SN74LV244A

SN74LV244A

ACTIVE

Eight-channel 2-V to 5.5-V buffers with tri-state outputs

Texas Instruments SN74LV244A Product Info

1 April 2026 0

Parameters

Technology family

LV-A

Supply voltage (min) (V)

2

Supply voltage (max) (V)

5.5

Number of channels

8

IOL (max) (mA)

16

Supply current (max) (µA)

20

IOH (max) (mA)

-16

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Package

SOIC (DW)-20-131.84 mm² 12.8 x 10.3

Features

  • V CC operation of 2 V to 5.5 V
  • Maximum t pd of 6.5 ns at 5 V
  • Typical V OLP (output ground bounce) <0.8 V at V CC = 3.3 V, T A = 25°C
  • Typical V OHV (output V OH undershoot) >2.3 V at V CC = 3.3 V, T A = 25°C
  • Support mixed-mode voltage operation on all ports
  • I off supports partial-power-down mode operation
  • Latch-up performance exceeds 250-mA per JESD 17
  • V CC operation of 2 V to 5.5 V
  • Maximum t pd of 6.5 ns at 5 V
  • Typical V OLP (output ground bounce) <0.8 V at V CC = 3.3 V, T A = 25°C
  • Typical V OHV (output V OH undershoot) >2.3 V at V CC = 3.3 V, T A = 25°C
  • Support mixed-mode voltage operation on all ports
  • I off supports partial-power-down mode operation
  • Latch-up performance exceeds 250-mA per JESD 17

Description

The SN74LV244A octal buffers and line drivers are designed for 2-V to 5.5-V V CC operation.

The SN74LV244A devices are designed specifically to improve both performance and density of the 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices are organized as two 4-bit line drivers with separate output-enable ( OE) inputs.

The SN74LV244A octal buffers and line drivers are designed for 2-V to 5.5-V V CC operation.

The SN74LV244A devices are designed specifically to improve both performance and density of the 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices are organized as two 4-bit line drivers with separate output-enable ( OE) inputs.

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