0
ACTIVE
Technology family |
LV-A |
Supply voltage (min) (V) |
2 |
Supply voltage (max) (V) |
5.5 |
Number of channels |
4 |
IOL (max) (mA) |
16 |
Supply current (max) (µA) |
20 |
IOH (max) (mA) |
-16 |
Input type |
Standard CMOS |
Output type |
3-State |
Features |
Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) |
Rating |
Automotive |
Operating temperature range (°C) |
-40 to 125 |
VQFN (RGY)-14-12.25 mm² 3.5 x 3.5
The SN74LV125A-Q1 quadruple bus buffer gate is designed for 2-V to 5.5-V VCC operation.
This device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
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