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SN74HCS596
  • SN74HCS596
  • SN74HCS596
  • SN74HCS596

SN74HCS596

ACTIVE

8-bit serial-in/parallel-out shift register

Texas Instruments SN74HCS596 Product Info

1 April 2026 0

Parameters

Configuration

Serial-in, Parallel-out

Bits (#)

8

Technology family

HCS

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

Schmitt-Trigger

Output type

Open-drain

Clock frequency (MHz)

75

IOL (max) (mA)

7.8

IOH (max) (mA)

-7.8

Supply current (max) (µA)

2

Features

Balanced outputs, High speed (tpd 10-50ns), Output register, Positive input clamp diode

Operating temperature range (°C)

-40 to 125

Rating

Catalog

Package

SOIC (D)-16-59.4 mm² 9.9 x 6

Features

  • Wide operating voltage range: 2 V to 6 V
  • Schmitt-trigger inputs allow for slow or noisy input signals
  • Low power consumption
    • Typical ICC of 100 nA
    • Typical input leakage current of ±100 nA
  • ±7.8-mA output drive at 6 V
  • Extended ambient temperature range: –40°C to +125°C, TA
  • Wide operating voltage range: 2 V to 6 V
  • Schmitt-trigger inputs allow for slow or noisy input signals
  • Low power consumption
    • Typical ICC of 100 nA
    • Typical input leakage current of ±100 nA
  • ±7.8-mA output drive at 6 V
  • Extended ambient temperature range: –40°C to +125°C, TA

Description

The SN74HCS596 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. All inputs include Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals. The storage register has parallel open-drain outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output (QH’) for cascading. When the output-enable (OE) input is high, the outputs are in a highimpedance state. Internal register data is not impacted by the operation of the OE input.

The SN74HCS596 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. All inputs include Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals. The storage register has parallel open-drain outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output (QH’) for cascading. When the output-enable (OE) input is high, the outputs are in a highimpedance state. Internal register data is not impacted by the operation of the OE input.

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