Product
0
LMG3411R050
  • LMG3411R050
  • LMG3411R050

LMG3411R050

ACTIVE

600-V 50mΩ GaN with integrated driver and cycle-by-cycle overcurrent protection

Texas Instruments LMG3411R050 Product Info

1 April 2026 3

Parameters

VDS (max) (V)

600

RDS(on) (mΩ)

50

ID (max) (A)

12

Features

Bottom-side cooled, Cycle-by-cycle overcurrent protection, Overtemperature protection

Rating

Catalog

Operating temperature range (°C)

-40 to 150

Package

VQFN (RWH)-32-64 mm² 8 x 8

Features

  • TI GaN FET reliability qualified with in-application hard-switching accelerated stress profiles
  • Enables high density power conversion designs
    • Superior system performance over cascode or stand-alone GaN FETs
    • Low inductance 8 mm x 8 mm QFN package for ease of design, and layout
    • Adjustable drive strength for switching performance and EMI control
    • Digital fault status output signal
    • Only +12 V unregulated supply needed
  • Integrated gate driver
    • Zero common source inductance
    • 20 ns Propagation delay for MHz operation
    • Trimmed gate bias voltage to compensate for threshold variations ensures reliable switching
    • 25 to 100V/ns User adjustable slew rate
  • Robust protection
    • Requires no external protection components
    • Overcurrent protection with less than 100 ns response
    • Greater than 150 V/ns Slew rate immunity
    • Transient overvoltage immunity
    • Overtemperature protection
    • Under voltage lock out (UVLO) Protection on all supply rails
  • Robust protection
    • LMG3410R050: Latched overcurrent protection
    • LMG3411R050: Cycle-by-cycle overcurrent protection
  • TI GaN FET reliability qualified with in-application hard-switching accelerated stress profiles
  • Enables high density power conversion designs
    • Superior system performance over cascode or stand-alone GaN FETs
    • Low inductance 8 mm x 8 mm QFN package for ease of design, and layout
    • Adjustable drive strength for switching performance and EMI control
    • Digital fault status output signal
    • Only +12 V unregulated supply needed
  • Integrated gate driver
    • Zero common source inductance
    • 20 ns Propagation delay for MHz operation
    • Trimmed gate bias voltage to compensate for threshold variations ensures reliable switching
    • 25 to 100V/ns User adjustable slew rate
  • Robust protection
    • Requires no external protection components
    • Overcurrent protection with less than 100 ns response
    • Greater than 150 V/ns Slew rate immunity
    • Transient overvoltage immunity
    • Overtemperature protection
    • Under voltage lock out (UVLO) Protection on all supply rails
  • Robust protection
    • LMG3410R050: Latched overcurrent protection
    • LMG3411R050: Cycle-by-cycle overcurrent protection

Description

The LMG341xR050 GaN power stage with integrated driver and protection enables designers to achieve new levels of power density and efficiency in power electronics systems. The LMG341x’s inherent advantages over silicon MOSFETs include ultra-low input and output capacitance, zero reverse recovery to reduce switching losses by as much as 80%, and low switch node ringing to reduce EMI. These advantages enable dense and efficient topologies like the totem-pole PFC.

The LMG341xR050 provides a smart alternative to traditional cascode GaN and standalone GaN FETs by integrating a unique set of features to simplify design, maximize reliability and optimize the performance of any power supply. Integrated gate drive enables 100 V/ns switching with near zero Vds ringing, less than 100 ns current limiting response self-protects against unintended shoot-through events, overtemperature shutdown prevents thermal runaway, and system interface signals provide self-monitoring capability.

Subscribe to Welllinkchips !
Your Name
* Email
Popular Posts
Featured Parts More >
Submit a request
CONTACT US
Company address

WELL LINK CHIPS GROUP CO.,LIMITED FLAT/RM 1802 BEVERLY HOUSE 93-107 LOCKHART ROAD WANCHAI HK

Send Enquiry
SEND e-MAIL
Office hour from 9am to 6pm ,
Monday through Friday, UTC/GMT +8