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CY74FCT273T
  • CY74FCT273T
  • CY74FCT273T

CY74FCT273T

ACTIVE

Octal D-Type Flip-Flops with Clear

Texas Instruments CY74FCT273T Product Info

1 April 2026 4

Parameters

Number of channels

8

Technology family

FCT

Supply voltage (min) (V)

4.75

Supply voltage (max) (V)

5.25

Input type

TTL, TTL-Compatible CMOS

Output type

CMOS, Push-Pull

Clock frequency (max) (MHz)

100

IOL (max) (mA)

64

IOH (max) (mA)

-32

Supply current (max) (µA)

200

Features

Partial power down (Ioff), Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Package

SOIC (DW)-20-131.84 mm² 12.8 x 10.3

Features

  • Function, Pinout, and Drive Compatible With FCT and F Logic
  • Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Fully Compatible With TTL Input and Output Logic Levels
  • CY54FCT273T
    • 32-mA Output Sink Current
    • 12-mA Output Source Current
  • CY74FCT273T
    • 64-mA Output Sink Current
    • 32-mA Output Source Current

  • Function, Pinout, and Drive Compatible With FCT and F Logic
  • Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Fully Compatible With TTL Input and Output Logic Levels
  • CY54FCT273T
    • 32-mA Output Sink Current
    • 12-mA Output Source Current
  • CY74FCT273T
    • 64-mA Output Sink Current
    • 32-mA Output Source Current

Description

The x92FCT273T devices consist of eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered-clock (CP) and master-reset (MR) inputs load and reset all flip-flops simultaneously. These devices are edge-triggered registers. The state of each D input (one setup time before the low-to-high clock transition) is transferred to the corresponding flip-flopx92s Q output. All outputs are forced low by a low logic level on the MR input.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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