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ADS52J65
  • ADS52J65
  • ADS52J65

ADS52J65

ACTIVE

8-channel 16-bit 125-MSPS analog-to-digital converter (ADC) with JESD204B interface

Texas Instruments ADS52J65 Product Info

1 April 2026 0

Parameters

Sample rate (max) (Msps)

125

Resolution (Bits)

16

Number of input channels

8

Interface type

JESD204B

Analog input BW (MHz)

250

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

560

Architecture

Pipeline

SNR (dB)

78

ENOB (Bits)

13

SFDR (dB)

85

Operating temperature range (°C)

-40 to 85

Input buffer

No

Package

VQFN (RGC)-64-81 mm² 9 x 9

Features

  • 16/14-Bit Resolution, 8/4-Channel ADC
  • Idle Signal-to-Noise Ratio (SNR):
    • 80dBFS for 16bit ADC
    • 79dBFS for 14bit ADC
  • Power dissipation at 125MSPS, 4CH per Lane:
    • 70mW/Ch for ADS52J65/66 (8CH ADC)
    • 82mW/Ch for ADS52J67/68 (4CH ADC)
  • Power dissipation at 62.5MSPS, 8CH per Lane:
    • 45mW/Ch for ADS52J65/66 (8CH ADC)
    • 65mW/Ch for ADS52J67/66 (4CH ADC)
  • Full-Scale Input: 2VPP
  • Full-Scale SNR at fIN = 10MHz:
    • 78dBFS for 16bit ADC
    • 77dBFS for 14bit ADC
  • Full-Scale SFDR: –85dBc at fin = 10MHz
  • Analog Input –3dB Bandwidth = 250MHz
  • Maximum Input Signal Frequency for 2VPP Input = 130MHz
  • Fast and Consistent Overload Recovery
  • Advanced Digital Features
    • Automatic DC Offset Correction
    • Digital Average
  • Digital I/Q Demodulator
    • Fractional Decimation Filter M = 1 to 63 With Increments of 0.25
    • Data Output Rate Reduction After Decimation
    • Power dissipation at 80MSPS and Decimation = 2
      • 64mW/Ch for ADS52J65/66 (8-CH ADC)
      • 91mW/Ch for ADS52J67/68 (4-CH ADC)
    • On-Chip RAM With 32 Preset Profiles
  • JESD204B Subclass 0, 1, and 2
    • 2, 4, or 8 Channels per JESD Lane
    • 10Gbps JESD Interface
    • Supports lane rate up to 12.8Gbps for short trace length (< 5 Inch)
  • 64-Pin Non-Magnetic 9 × 9mm Package
  • 16/14-Bit Resolution, 8/4-Channel ADC
  • Idle Signal-to-Noise Ratio (SNR):
    • 80dBFS for 16bit ADC
    • 79dBFS for 14bit ADC
  • Power dissipation at 125MSPS, 4CH per Lane:
    • 70mW/Ch for ADS52J65/66 (8CH ADC)
    • 82mW/Ch for ADS52J67/68 (4CH ADC)
  • Power dissipation at 62.5MSPS, 8CH per Lane:
    • 45mW/Ch for ADS52J65/66 (8CH ADC)
    • 65mW/Ch for ADS52J67/66 (4CH ADC)
  • Full-Scale Input: 2VPP
  • Full-Scale SNR at fIN = 10MHz:
    • 78dBFS for 16bit ADC
    • 77dBFS for 14bit ADC
  • Full-Scale SFDR: –85dBc at fin = 10MHz
  • Analog Input –3dB Bandwidth = 250MHz
  • Maximum Input Signal Frequency for 2VPP Input = 130MHz
  • Fast and Consistent Overload Recovery
  • Advanced Digital Features
    • Automatic DC Offset Correction
    • Digital Average
  • Digital I/Q Demodulator
    • Fractional Decimation Filter M = 1 to 63 With Increments of 0.25
    • Data Output Rate Reduction After Decimation
    • Power dissipation at 80MSPS and Decimation = 2
      • 64mW/Ch for ADS52J65/66 (8-CH ADC)
      • 91mW/Ch for ADS52J67/68 (4-CH ADC)
    • On-Chip RAM With 32 Preset Profiles
  • JESD204B Subclass 0, 1, and 2
    • 2, 4, or 8 Channels per JESD Lane
    • 10Gbps JESD Interface
    • Supports lane rate up to 12.8Gbps for short trace length (< 5 Inch)
  • 64-Pin Non-Magnetic 9 × 9mm Package

Description

The 8/4-channel, 16/14-bit ADS52J6x analog-to-digital converter (ADC) uses CMOS process and remarkable circuit techniques. The device is designed to operate at low power and give very high signal-to-noise ratio (SNR) performance with a 2-Vpp full-scale input. The ADS52J65 device gives 80dBFS idle SNR and 78dBFS full scale SNR at 5MHz. The large input bandwidth of 250MHz makes the device well suited for a wide range of applications, such as high frequency medical ultrasound, magnetic resonance imaging, multi-channel data acquisition, flow cytometry, and hematology analyzer. The ADC integrates an internal reference trimmed to match across devices.

ADS52J6x has advanced digital features, including a digital I/Q demodulator with fractional decimation filter. The ADC data from each channel is encoded using an 8B to 10B format and is sent as a SerDes data stream using current-mode logic (CML) outputbuffers, as per the JESD204B standard. The ADC data from all eight channels can be output over a single CML buffer (1-lane SerDes) with the data rate limited to a maximum of 12.8Gbps. Using SerDes outputs reduces the number of interface lines. This, together with the low-power design, enables eight channels to be packaged in a 9mm × 9mm VQFN allowing high system integration densities. ADS52J6x also supports modes where all ADC data is sent over four CML buffers (4-Lane SerDes), reducing the SerDes data rate per lane for low-cost FPGAs. The ADS52J6x is available in a non-magnetic VQFN package that does not create any magnetic artifact. The device is specified over –40°C to +85°C.

The 8/4-channel, 16/14-bit ADS52J6x analog-to-digital converter (ADC) uses CMOS process and remarkable circuit techniques. The device is designed to operate at low power and give very high signal-to-noise ratio (SNR) performance with a 2-Vpp full-scale input. The ADS52J65 device gives 80dBFS idle SNR and 78dBFS full scale SNR at 5MHz. The large input bandwidth of 250MHz makes the device well suited for a wide range of applications, such as high frequency medical ultrasound, magnetic resonance imaging, multi-channel data acquisition, flow cytometry, and hematology analyzer. The ADC integrates an internal reference trimmed to match across devices.

ADS52J6x has advanced digital features, including a digital I/Q demodulator with fractional decimation filter. The ADC data from each channel is encoded using an 8B to 10B format and is sent as a SerDes data stream using current-mode logic (CML) outputbuffers, as per the JESD204B standard. The ADC data from all eight channels can be output over a single CML buffer (1-lane SerDes) with the data rate limited to a maximum of 12.8Gbps. Using SerDes outputs reduces the number of interface lines. This, together with the low-power design, enables eight channels to be packaged in a 9mm × 9mm VQFN allowing high system integration densities. ADS52J6x also supports modes where all ADC data is sent over four CML buffers (4-Lane SerDes), reducing the SerDes data rate per lane for low-cost FPGAs. The ADS52J6x is available in a non-magnetic VQFN package that does not create any magnetic artifact. The device is specified over –40°C to +85°C.

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