• Four Input Clocks: one crystal/CMOS input, two differential/CMOS inputs, one single-ended/CMOS input
• Any input frequency up to 1035MHz (up to 300MHz for CMOS)
• Clock selection by pin or register control
• Up to 3 Differential Outputs (Up to 6 CMOS)
• Output frequencies are any integer divisor up to 232 of the input frequency (CMOS 250MHz max)
• Each output has independent dividers
• Low additive jitter <200fs RMS (12kHz-20MHz, for input frequencies above 100MHz)
• Outputs are CML or 2xCMOS, can interface to LVDS, LVPECL, HSTL, SSTL and HCSL
• In 2xCMOS mode, the P and N pins can be different frequencies (e.g. 125MHz and 25MHz)
• Per-output supply pin with CMOS output voltages from 1.5V to 3.3V
• Precise output alignment circuitry and per-output phase adjustment
• Per-output enable/disable and glitch-less start/stop (stop high or low)
• Automatic self-configuration at power-up from internal EEPROM; up to four configurations, pin-selectable
• Crystal interface for frequency synthesis up to 60MHz
• Four general-purpose I/O pins, each with many status and control options
• SPI or I2C processor Interface
• Tiny 5x5mm QFN package

The ZL40255 SmartBuffer™ is a flexible, programmable fanout buffer IC. The ZL40255 can select from 1 of 4 input clocks and provide as many as 3 differential or 6 CMOS outputs. Each output can provide format conversion, integer frequency division, and skew adjustment. Flexible any-format outputs simplify design. Automatic self-configuration after power-up or reset.