Highlights
• Ultra Precise Timing for 5G Radio Access Networks
• Two independent DPLL clock channels plus three additional DPLLs for NCO Hybrid, Split XO and redundant oscillator modes
• Five output synthesizers
• Any-to-any frequency conversion per channel
• Inputs: up to 8 differential or single-ended
• Outputs: up to 6 differential, up to 12 CMOS
• Output jitter 100 fs RMS typical for 156.25 MHz 12 kHz to 20 MHz
• Core power consumption <0.9W

Physical-layer frequency synchronization
• Hitless reference switching

General Features
• Automatic self-configuration at power-up from internal Flash memory, 7 configurations
• Input-to-output alignment <100 ps
• Numerically controlled oscillator behavior in each DPLL and each synthesizer
• Easy-to-configure design requires no external VCXO or loop filter components
• 5 GPIO pins with many possible behaviors, each REF can be GPI, each OUT can be GPO
• SPI or I2C processor Interface
• 1.8V and 3.3V core VDD voltages
• Easy-to-use evaluation/programming software
• MiToDSync 1-wire time-of-day interface in/out
• MiToDBasic 3-wire time-of-day interface out

The ZL30642AS is a feature-rich line card solution with up to five independent DPLLs, five extremely low output jitter synthesizers and embedded time-of-day (eToD) features. The eToD features include a 3-wire MiToDBasic output interface and a 1-wire MiToDSync input/output interface.This solution is ideal for line card timing applications such as routers, switches, optical transparent network and 4G/5G wireless base stations.

We also have ZL3063x as SyncE Timing Card Synchronizer, such as ZL30634A, or ZL3073x as SyncE&1588 Timing Card Synchronizer, such as ZL30735A, to form full SyncE&IEEE1588 Timing solution.