Additional Features
• Any-to-any frequency conversion per channel
• Inputs: up to 6, differential or singled-ended
• Outputs: up to 10 differential, up to 20 CMOS
• Output jitter <150fs RMS 156.25MHz 12k-20M
• Core power consumption <0.9W

Input Clocks
• Any input frequency from 1kHz to 1250MHz
• Per-input activity and frequency monitoring
• Automatic or manual reference switching
• Revertive or nonrevertive switching
• Any input can be a 0.5Hz to 8kHz Sync input for Ref+Sync frequency/phase/time locking
• Input phase measurement, 1ps resolution
• Per-input phase adjustment, 1ps resolution DPLLs

2 DPLL Channels
• Hitless reference switching
• Per-DPLL phase adjustment, 1ps resolution
• Programmable bandwidth, tracking range, phase-slope limiting and other advanced features
• Locking to gapped-clock input signals

Output Clocks
• Any frequency 0.5Hz to 750MHz
• Each OUTP/N pair can be LVDS, LVPECL, 2xCMOS, Low-Vcm or programmable differential
• In 2xCMOS mode, the P and N pins can be different frequencies (e.g. 125MHz and 25MHz)
• VDD per output pair, CMOS voltages 1.8V-3.3V
• Per-synth phase adjustment, 1ps resolution
• Per-output duty cycle adjustment
• Precise output alignment circuitry and peroutput phase adjustment
• Per-output enable/disable and glitchless start/stop (stop high or low)

Local Oscillator
• Operates from a single oscillator 9.72-400MHz

General Features
• Automatic self-configuration at power-up from internal Flash memory, 7 configurations
• Input-to-output alignment <100ps
• Numerically controlled oscillator behavior in each DPLL and each synthesizer
• Easy-to-configure design requires no external VCXO or loop filter components
• 5 GPIO pins with many possible behaviors, each REF can be GPI, each OUT can be GPO
• SPI or I2C processor Interface
• 1.8V and 3.3V core VDD voltages
• Easy-to-use evaluation/programming software

The ZL30273 is a feature-rich jitter attenuator with DPLLs and five extremely low output jitter synthesizers. This device is ideal for frequency conversion, jitter attenuation and frequency synthesis in a wide variety of equipment types requiring low jitter (<150fs) and multiple frequency families

Other devices in this family include ZL30731, ZL30732, ZL30733, ZL30734, ZL30631, ZL30632, ZL30633, ZL30634, ZL30635, ZL30641, ZL30642, ZL30643, ZL30644, ZL30645 and ZL30640 which are targeted for 5G SyncE and IEEE1588 timing card and line card applications.