0
In Production
Description |
÷2, 2x2;1 Output |
Input |
ECL/PECL |
Output |
ECL/PECL |
Supply Voltage |
3.3/5V |
Max Freq (GHz) |
4 |
Icc (mA) |
0 |
Max Within Device Skew (ps) |
- |
OE |
False |
Input Mux |
False |
Number Of Outputs |
0 |
Max Prop Delay (ps) |
440 |
The SY89312V is an integrated ÷2 divider with differential clock inputs. It is functionally equivalent to the SY100EP32V but in an ultra-small 8-lead MLF® package that features a 70% smaller footprint.The VBB pin, an internally generated voltage supply, is available for this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also bias AC-coupled inputs. When used, decouple VBB and VCC via a 0.01µF capacitor and limit current sourcing or sinking to 0.5mA. When not used, VBB should be left open.The reset pin is asynchronous and is asserted when it is high. Upon power-up, the internal flip-flops will be in a random state; the reset allows for the synchronous use of multiple SY89312Vs in a system.
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