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In Production
Description |
D Flip-Flop with Reset and Differential Clock |
Input |
ECL |
Output |
ECL |
Supply Voltage |
3.3/5 |
Max Freq (GHz) |
3 |
Icc (mA) |
0 |
OE |
False |
Input Mux |
False |
Number Of Outputs |
0 |
Max Prop Delay (ps) |
320 |
The SY10EP51V is a D flip-flop with reset and differential clock. The device is pin and functionally equivalent to the EL51 device.The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when CLK is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the CLK. The differential clock inputs of the EP51V allow the device to be used as a negative edge triggered flip-flop.The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to VEE and the /CLK input will be biased a VCC/2.
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