0
In Production
Description |
5V/3.3V ÷2 Divider |
Input |
LVPECL |
Supply Voltage |
3.3/5 |
Max Freq (GHz) |
0 |
Icc (mA) |
0 |
OE |
False |
Input Mux |
False |
Number Of Outputs |
0 |
Max Prop Delay (ps) |
630 |
The SY100EL32V is an integrated divide by 2 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC-coupled interface to the device. If used, the VBB output should be bypassed to ground with a 0.01 µF capacitor. Also note that the VBB is designed to be used as an input bias on the EL32V only; the VBB output has limited current sink and source capability. The Reset pin is asynchronous and is asserted on the rising edge. Upon power-on, the internal flip-flop will attain a random state. The Reset allows for the synchronization of multiple EL32Vs in a system.