0
In Production
Description |
1:9 CMOS Fanout Buffer 1.8-3.3V |
Input |
LVCMOS |
Output |
LVCMOS |
Supply Voltage |
2.5/3.3 |
Max Freq (GHz) |
0.15 |
Icc (mA) |
0 |
Max Within Device Skew (ps) |
250 |
OE |
True |
Input Mux |
False |
Input (MHz) |
DC |
Number Of Outputs |
9 |
Buffer Type |
Fanout |
Fanout |
1:9 |
Max Prop Delay (ps) |
9200 |
The PL133-97 is an advanced fanout buffer design for high performance, low-power, small form factor applications. The PL133-97 accepts a reference clock input from DC to 150 MHz and provides 9 outputs of the same frequency.The PL133-97 is offered in a QFN-16L 3mm x 3mm package and it offers the best phase noise, additive jitter performance, and lowest power consumption of any comparable IC. The PL133-97 outputs can be disabled to a high impedance (tri-state) by pulling low the OE pin. When the OE pin is high, the outputs are enabled and follow the REF input signal. When the OE pin is left open, a pull-up resistor on the chip will default the OE pin to logic 1 so the outputs are enabled.
WELL LINK CHIPS GROUP CO.,LIMITED FLAT/RM 1802 BEVERLY HOUSE 93-107 LOCKHART ROAD WANCHAI HK
