0
In Production
Buffer Type |
Zero Delay |
Fanout |
1:9 |
Icc (mA) |
0 |
Input |
LVCMOS |
Input (MHz) |
10-220 |
InputMux |
0 |
Output Frequency (Max) (GHz) |
0 |
No. of outputs |
9 |
OE |
0 |
Output |
LVCMOS |
The PL123E-09 (-09H for High Drive) is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks. It has two low-skew output banks, of 4 outputs each, that are synchronized with the input. Control of the two banks of outputs is achieved by using the S1 and S2 inputs as shown in the Selector Definition table on page 2 of the datasheet.The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than ±100ps, the device acts as a zero delay buffer. The input output propagation delay can be advanced or delayed by adjusting the load on the CLKOUT pin.These parts are not intended for 5V input-tolerant applications.
WELL LINK CHIPS GROUP CO.,LIMITED FLAT/RM 1802 BEVERLY HOUSE 93-107 LOCKHART ROAD WANCHAI HK
