Core:
• Arm® Cortex®-M4F CPU running at up to 120 MHz:
• 4 KB combined instruction cache and data cache
• 8-Zone Memory Protection Unit (MPU)
• Floating Point Unit (FPU)

Memories
• 1 MB in-system self-programmable Flash with Error Correction Code (ECC)
• 256 KB SRAM main memory with Error Correction Code (ECC)
• Up to 4 KB of Tightly Coupled Memory (TCM)
• 8 KB additional Backup SRAM

Low-Power and Power Management
• Idle, Standby, Hibernate, Backup, and Off sleep modes.
• Sleepwalking peripherals
• Battery backup support

Security
• One Advanced Encryption System (AES) with 256-bit key length and up to 2 MB/s data rate
• ECB, CBC, CFB, OFB, CTR modes of operation
• True Random Number Generator (TRNG)
• Public Key Cryptography Controller (PUKCC)
• RSA, DSA
• Elliptic Curves Cryptography (ECC) ECC GF(2n), ECCGF(p)
• Integrity Check Module (ICM) based on Secure Hash Algorithm (SHA1, SHA224, SHA256), DMA assisted.

Hardware Security Module
• Secure boot support: Validation of host code image and host code signature validation
• Secure update support for host code: Secure encryption key storage and image decryption
• X.509 Certificate storage, parsing, validation, and revocation, supporting both ECC and RSA
• High-speed SHA256, HMAC and AES-CMAC engines
• P224, P256 and P384 Elliptic Curve – ECDSA Sign/Verify
• ECDH support for P256 & P224 Curves
• ECBD support for P224 Curve
• SECP256K1 (Bitcoin/Blockchain curve) ECDSA support
• 256-bit Brainpool Elliptic Curve support – ECDSA, ECDH
• RSA - 2048 Sign/Verify, 3072 Verify, 1024 Encrypt/Decrypt
• 256 bit key generation and derivation
• 2048 bit RSA key generation and derivation
• Elliptic Curve Diffie Hellman (ECDH/ECDHE) Key Agreement
• NIST SP800-90 Random Number Generator (RNG)
• Internal symmetric and asymmetric key generation

Peripherals/Timers
• 32-channel Event System
• Up to Eight Configurable Serial Communication Interfaces (SERCOM),
• Eight 16-bit Timers/Counters (TC) each configurable as 16-bit ,8-bit and 32-bit TC
• Two 24-bit Timer/Counters for Control (TCC), with extended functions:
• Three 16-bit Timer/Counters for Control (TCC) with extended
• 32-bit Real Time Counter (RTC) with clock/calendar function
• Up to 5 wake-up pins with tamper detection and debouncing filter

Advanced Analog:
• Dual 12-bit, 1 MSPS Analog-to-Digital Converter (ADC) with up to 16 channels each
• Dual 12-bit, 1 MSPS Analog-to-Digital Converter (ADC) with up to 16 channels each
• Two Analog Comparators (AC) with Window Compare function

Communication Interfaces:
• One two-channel Inter-IC Sound Interface (I2S)
• Parallel Capture Controller (PCC), up to 14 bits wide
• Peripheral Touch Controller (PTC) with Up to 32 self-capacitance and up to 256 mutual capacitance Channels
• Two SD/MMC Host Controller (SDHC)
• 32-channel Direct Memory Access Controller (DMAC)
• One Quad I/O Serial Peripheral Interface (QSPI)
• One 10/100 Mbps Ethernet MAC with dedicated DMA
• Two Controller Area Network (CAN) with Support for CAN 2.0A/CAN 2.0B and CAN-FD (ISO
• One Full-Speed (12 Mbps) Universal Serial Bus (USB) 2.0 With Embedded host and device function
• Clock Management/System
• 32.768 kHz crystal oscillator (XOSC32K) with Clock failure detection
• Two 8 MHz to 48 MHz crystal oscillator (XOSC) with Clock failure detection
• 32.768 kHz ultra-low-power internal oscillator (OSCULP32K)
• Power-on Reset (POR) and Brown-out Detection (BOD)

Debugger Development Support
• Two-pin Serial Wire Debug (SWD) programming and debugging interface.
• Six hardware breakpoints and four data watchpoints

PIC32CX  high performance micro-controller series features a 32-bit ARM® Cortex®-M4 processor with Floating Point Unit (FPU), running up to 120 MHz ,up to 1 MB Dual Panel Flash with ECC, and up to 256 KB of SRAM with ECC .It also adds a 10/100 Ethernet MAC and 2 CAN-FD ports targeted for industrial automation ,automotive applications and general purpose applications requiring Wired connectivity.

Common Criteria Joint Interpretation Library (JIL) high-rated secure subsystem provides hardware-based cryptographic key storage and crypto accelerators for multiple asymmetric, symmetric, and hashing security protocols. The secure subsystem combined with MCU's integrated security features supports an ultra-secure method for key agreement, sign-verify authentication for automotive in-vehicle networking, industrial and consumer applications. The security features in the PIC32CX SG MCUs protect against remote digital attacks while the integrated secure subsystem provides extra security with physical anti-tampering and side channel attack protections to block access to embedded system credentials. Usecases Supported include code authentication (aka secure boot), message authentication via MAC generation, trusted firmware updates, multiple key management protocols including TLS and other root-of-trust based operations.

The documentation and additional resources related to the secure subsystem is available under NDA. Contact your local Microchip sales team for more information or our Client Success Team (Schedule a Call) to get assistance with your design.

Key features

·         Quad Serial Peripheral Interface(QSPI) with Execute in Place (XIP) Support.

·         Up to 2 Secure Digital Host Controller (SDHC)

·    10/100 Ethernet MAC with IEEE 1588 support.

·        Up to 2 CAN-FD Interface.

·         Inter-IC Sound(I2S)Controller for Audio

·         Peripheral Touch Controller (PTC) supporting up to 256 channels of capacitive touch .

·         Full speed USB with embedded Host/device.

·         Integrated security including Asymmetric and Symmetric Crypto hardware acceleration

On Chip Secure Subsystem/Hardware Security Module (HSM)

• Secure boot support: Validation of host code image and host code

signature validation

• Secure update support for host code: Secure encryption key

storage and image decryption

• X.509 Certificate storage, parsing, validation and revocation,

supporting both ECC and RSA

• Asymmetric (RSA/ECC) and Symmetric (SHA)Hardware Crypto Accelerators.

• 256 bit ECC/ 2048 bit RSA key generation and derivation

• NIST SP800-90 Random Number Generator (RNG)

• ECDSA Sign/verify, ECDH Support

Protection, allowing secure boot support

·         Serial communication (SERCOM) ports configurable as UART/USART, ISO 7816, SPI or I²C 

Supported by MPLAB X IDE and MPLAB Harmony.