0
S28HS02GTFPBHM050
  • S28HS02GTFPBHM050

S28HS02GTFPBHM050

Active and preferred

The S28HS02GTFPBHM050 is a 2 Gb SEMPER™ Flash using MIRRORBIT™ technology in a dual-die package. It supports Octal (up to 400 MBps DDR, 166 MBps SDR) and SPI interfaces, JEDEC JESD251 compliant, with a 1.8 V supply. Safety features include ISO26262 ASIL B compliance, ECC for single-bit correction and double-bit detection, Endurance flex architecture, CRC-based data integrity, and SafeBoot initialization failure detection.

Infineon Technologies S28HS02GTFPBHM050 Product Info

16 April 2026 0

Parameters

Classification

ISO 26262-compliant

Density

2 GBit

Family

HS-T

Interface Bandwidth

333 MByte/s

Interface Frequency (SDR/DDR) (MHz)

- / 166

Interfaces

Octal

Lead Ball Finish

Sn/Ag/Cu

Operating Temperature range

-40 °C to 125 °C

Operating Voltage range

1.7 V to 2 V

Operating Voltage

1.8 V

Peak Reflow Temp

260 °C

Planned to be available until at least

2037

Qualification

Automotive

Apps

Domain controller for ADAS & autonomous driving, Automotive LED lighting systems

Features

  • Embedded Hamming ECC for error correction
  • 16-byte data unit with 1-bit correction,
  • ECC error reporting via status registers
  • Endurance flex architecture with wear
  • Configurable high endurance or long retention
  • JEDEC JESD251 xSPI compliant interface
  • Supports Octal and legacy SPI interfaces
  • SDR and DDR modes for high-speed access
  • Flexible sector architecture: 4 KB and 256 KB
  • Page programming buffer: 256 or 512 bytes
  • Data integrity check with CRC
  • SafeBoot for initialization and corruption

Description

  • ECC improves data reliability and safety
  • 2-bit error detection prevents data
  • Status registers enable fast diagnostics
  • Wear leveling extends device lifetime
  • Flexible endurance/retention for various
  • xSPI compliance ensures broad compatibility
  • Octal/SPI support eases system integration
  • High-speed modes boost data throughput
  • Flexible sectors fit diverse memory maps
  • Large buffer increases programming speed
  • CRC checks enhance data integrity
  • SafeBoot ensures secure startup

Subscribe to Welllinkchips !
Your Name
* Email
Submit a request