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S25FS128SAGNFB100
  • S25FS128SAGNFB100

S25FS128SAGNFB100

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Infineon Technologies S25FS128SAGNFB100 Product Info

16 April 2026 0

Features

  • SPI interface with multi I/O support
  • Double data rate (DDR) read option
  • 24- or 32-bit addressing modes
  • Burst wrap, continuous (XIP), QPI modes
  • Hardware ECC with single-bit correction
  • Hybrid and uniform sector erase options
  • 256- or 512-byte page program buffer
  • 100,000 program-erase cycles minimum
  • 20 year data retention minimum
  • Supply voltage: 1.7 V to 2.0 V
  • Operating temp: –40°C to +125°C
  • JEDEC JESD216B SFDP and CFI compliant

Description

  • Multi I/O enables faster data transfer
  • DDR read boosts throughput for demanding apps
  • Flexible addressing supports large memories
  • XIP/QPI modes enable direct code execution
  • ECC improves data reliability and integrity
  • Multiple erase options ease system
  • Large page buffer accelerates programming
  • High endurance supports frequent updates
  • Long retention ensures data stays safe
  • Low voltage reduces power consumption
  • Wide temp range fits harsh environments
  • JEDEC compliance ensures compatibility

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