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CYT2B93CACQ0AZEGST
  • CYT2B93CACQ0AZEGST

CYT2B93CACQ0AZEGST

Active and preferred

The CYT2B93CACQ0AZEGST is an automotive microcontroller from the TRAVEO T2G CYT2B9 Series, featuring dual ARM cores (Cortex-M4F at 160 MHz and Cortex-M0+), single-precision FPU, HSM security, and ASIL-B functional safety. It operates from 2.7 to 5.5 V across -40°C to 125°C, with 2112 KB flash, 128 KB work flash, 256 KB SRAM, 27 ADC channels, 49 GPIO, and 5 CAN-FD. ISO 26262 and ISO 21434-ready, RoHS and halogen free. Secure boot and watchdog enable reliable control.

Infineon Technologies CYT2B93CACQ0AZEGST Product Info

16 April 2026 0

Parameters

16bit TCPWM (Motor control)

11

16bit TCPWM

63

32bit TCPWM

8

ADC Channel

27

ASIL/SIL support

ASIL-B

CAN-FD

5

Classification

ISO 26262-compliant

CXPI

2

Cybersecurity Classification

ISO 21434-compliant

Debug Interface

SWD/JTAG/Trace

DMA Channels

92/44/4

eMMC

0

eSHE/HSM

HSM

Ethernet Ports

0

Ethernet speed

NA

External Interrupt channel

49

Flash Security

Yes

Flash

2112 kByte

FlexRayTM

0

Floating Point Unit

Single precision

GPIO

49

I2S

NA

LIN

7

Main Core frequency

160 MHz

Main Core type/Crypto Core type

ARM_CM4F/CM0+

MPU

Yes

Operating temperature range TA

-40°C to 125°C

PPU

Yes

RC-OSC

Yes

RTC channel

1

SCB Blocks

7

Smart IOs

9

SMIF (SPI/HyperBus)

NA

SRAM

256 kByte

Supply Voltage

2.7 to 5.5

Temperature sensor

Yes

Watchdog

Yes

Work Flash

128 kByte

Features

  • Dual CPU: Cortex-M4F 160 MHz, Cortex-M0+ 100
  • Single-precision FPU and DSP on Cortex-M4F
  • 2112 KB code-flash, 128 KB work-flash, 256 KB
  • Hardware inter-processor communication
  • Three DMA controllers: P-DMA0, P-DMA1, M-DMA0
  • Crypto engine: AES, 3DES, RSA, ECC, SHA,
  • Functional safety: MPU, SMPU, PPU, WDT, MCWDT
  • Low-power modes: Active, Sleep, Deep Sleep,
  • Up to 8 CAN FD channels (up to 8 Mbps), ISO
  • Up to 8 SCB (I2C, SPI, UART), 12 LIN channels
  • 12-bit SAR ADC, 1 Msps, up to 39 channels
  • Debug: SWD/JTAG, on-chip debug, trace support

Description

  • Dual CPUs enable real-time and secure tasks
  • FPU/DSP boost math and signal processing
  • Large flash/SRAM support complex applications
  • Hardware IPC ensures fast, safe multitasking
  • DMA controllers speed up data transfers
  • Crypto engine secures data and authentication
  • Safety features protect against faults
  • Low-power modes extend battery/system life
  • CAN FD, SCB, LIN enable flexible connectivity
  • High-speed ADC supports precise measurements
  • On-chip debug simplifies development
  • ISO CAN FD compliance ensures

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