CYPT2644KV18-250GCMB

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Infineon Technologies CYPT2644KV18-250GCMB Product Info

16 April 2026 0

Architecture	QDR-II+, ODT
Bank Switching	N
Burst Length (Words)	2
Data Width	x 36
Density	144 MBit
Device weight	6152.8 mg
ECC	N
Family	QDR-II+, ODT
Frequency	250 MHz
Interfaces	Parallel
Lead Ball Finish	Sn/Pb
On-Die Termination	Y
Operating Temperature range	-55 °C to 125 °C
Operating Voltage range	1.7 V to 1.9 V
Organization (X x Y)	4Mb x 36
Peak Reflow Temp	220 °C
Planned to be available until at least	2033
Qualification	Military
Read Latency (Cycles)	2
Real Time Clock	N
Watchdog	N

144 Mb density, 4M x 36 with two-word burst mode
250MHz max frequency / 36 Gbps throughput
Two independent unidirectional data ports for concurrent r/w transactions
Double Data Rate (DDR) port
Output impedance matching input (ZQ) matches the device outputs to system data bus impedance
Memory core bit-interleaving to eliminate multi-bit errors
On-die termination (ODT)
1.5 V to 1.8 V HSTL I/O signaling standards
1.7 V to 1.9 V operating voltage range
–55°C to +125°C military temperature grade
165-ball ceramic CGA (CCGA)
PROTOTYPE
For flight devices, order QML-V part number 5962R1821501VXF
Controller RTL IP cores with embedded EDAC are available for Xilinx and Microchip FPGAs

Dev kit available, to learn more: QDR®-II+ mezzanine board (P/N: CYDK-QDRII-NODT)

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