Product
0
CY7C4142KV13-106FCXC
  • CY7C4142KV13-106FCXC

CY7C4142KV13-106FCXC

Active and preferred

The QDR™-IV XP (Xtreme Performance) SRAM is a high-performance memory device optimized to maximize the number of random transactions per second by the use of two independent bidirectional data ports. These ports are equipped with DDR interfaces and designated as port A and port B respectively. Accesses to these two data ports are concurrent and independent of each other. Access to each port is through a common address bus running at DDR. The control signals are running at SDR and determine if a read or write should be performed.

Infineon Technologies CY7C4142KV13-106FCXC Product Info

16 April 2026 0

Parameters

Architecture

QDR-IV

Bank Switching

Y

Burst Length (Words)

2

Data Width

x 36

Density

144 MBit

ECC

Y

Family

QDR-IV

Frequency

1066 MHz

Interfaces

Parallel

Lead Ball Finish

Sn/Ag/Cu

On-Die Termination

Y

Operating Temperature range

0 °C to 70 °C

Operating Voltage range

1.26 V to 1.34 V

Organization (X x Y)

4Mb x 36

Peak Reflow Temp

260 °C

Planned to be available until at least

2031

Qualification

Commercial

Read Latency (Cycles)

8

Features

  • 144 Mbit density (8M × 18, 4M × 36)
  • Total Random Transaction Rate of 2132 MT/s
  • Maximum operating frequency of 1066 MHz
  • Read latency of 8.0 clock cycles
  • Write latency of 5.0 clock cycles
  • Eight-bank architecture enables 1 access per bank per cycle
  • Two-word burst on all accesses
  • Dual independent bidirectional data ports

Subscribe to Welllinkchips !
Your Name
* Email
Popular Posts
Featured Parts More >
Submit a request
CONTACT US
Company address

WELL LINK CHIPS GROUP CO.,LIMITED FLAT/RM 1802 BEVERLY HOUSE 93-107 LOCKHART ROAD WANCHAI HK

Send Enquiry
SEND e-MAIL
Office hour from 9am to 6pm ,
Monday through Friday, UTC/GMT +8