0
Active and preferred
Architecture |
QDR-IV |
Bank Switching |
N |
Burst Length (Words) |
2 |
Data Width |
x 36 |
Density |
144 MBit |
ECC |
Y |
Family |
QDR-IV |
Frequency |
667 MHz |
Interfaces |
Parallel |
Lead Ball Finish |
Sn/Ag/Cu |
On-Die Termination |
Y |
Operating Temperature range |
0 °C to 70 °C |
Operating Voltage range |
1.26 V to 1.34 V |
Organization (X x Y) |
4Mb x 36 |
Peak Reflow Temp |
260 °C |
Planned to be available until at least |
2031 |
Qualification |
Commercial |
Read Latency (Cycles) |
5 |
WELL LINK CHIPS GROUP CO.,LIMITED FLAT/RM 1802 BEVERLY HOUSE 93-107 LOCKHART ROAD WANCHAI HK
