0
Architecture |
DDR-II+ CIO |
Bank Switching |
N |
Burst Length (Words) |
2 |
Data Width |
x 18 |
Density |
144 MBit |
ECC |
N |
Family |
DDR-II+ CIO |
Frequency |
550 MHz |
Interfaces |
Parallel |
Lead Ball Finish |
Sn/Ag/Cu |
On-Die Termination |
N |
Operating Temperature range |
0 °C to 70 °C |
Operating Voltage range |
1.7 V to 1.9 V |
Organization (X x Y) |
8Mb x 18 |
Peak Reflow Temp |
260 °C |
Qualification |
Commercial |
Read Latency (Cycles) |
2.5 |
WELL LINK CHIPS GROUP CO.,LIMITED FLAT/RM 1802 BEVERLY HOUSE 93-107 LOCKHART ROAD WANCHAI HK
