Analog Devices MAX5855 Product Info

• Simplifies RF Design and Enables New Communication Architectures
• Eliminates I/Q Imbalance and LO Feedthrough
• Enables Multi-Band RF Modulation
• Direct RF Synthesis of 1GHz Bandwidth
  • 4.9152Gsps DAC Output Update Rate
  • High-Performance 14-Bit RF DAC Core
  • Digital Baseband I/Q with 4x Interpolation
  • Digital Quadrature Modulator + NCO for Full Agility
  • Sub-1Hz NCO Resolution
  • Integrated Clock Multiplying PLL + VCO
• Flexible and Configurable
• 5-Lane JESD204B Input Data Interface
• Subclass-0 Compliant
• 9.8304Gbps Per Lane
• Divided Reference Clock Output
• SPI Interface for Device Configuration

The MAX5855 high-performance, interpolating and modulating, 16-bit, 4.9Gsps RF DAC can directly synthesize up to 1000MHz of instantaneous bandwidth from DC to frequencies greater than 2.45GHz. The device is optimized for cable access and digital video broadcast applications and meets spectral emission requirements for a broad set of radio transmitters and modulators including DOCSIS 3.1/3.0, DVB-C/C2, DVB-T2, DVB-S2X, ISDB-T, and EPoC.

The device integrates interpolation filters, a digital quadrature modulator, a numerically controlled oscillator (NCO), clock multiplying PLL + VCO and a 14-bit RF DAC core. The 4x linear phase interpolation filter simplifies reconstruction filtering, while enhancing passband dynamic performance, and reducing the input data bandwidth required from an FPGA. The NCO allows for fully agile modulation of the input baseband signal for direct RF synthesis.

The MAX5855 input interface accepts 16-bit input data by way of a five-lane, JESD204B SerDes data input interface that is Subclass-0 compliant and operates at a data rate of 9.8304Gbps.

The MAX5855 clock input has a flexible interface that accepts a differential sine-wave or square-wave reference input clock signal at 245.75MHz, 491.52MHz, or 983.04MHz. A clock multiplying PLL and VCO is used to internally generate the 4.9152GHz sampling clock from the reference clock. The device provides a divided reference clock output to ensure synchronization between the data source and the DAC.

The integrated RF DAC uses a differential current-steering architecture that includes a differential 50Ω internal termination and can produce a 3dBm full-scale output signal level on a 50Ω external load. Operating from 1.0V and 1.8V power supplies, the device consumes 2.7W