LTC6952

LAST TIME BUY

Ultralow Jitter, 4.5GHz PLL with 11 Outputs and JESD204B / JESD204C Support

Analog Devices LTC6952 Product Info

10 February 2026 6

Features

JESD204B/C, Subclass 1 SYSREF Signal Generation
Low Noise Integer-N PLL
Additive Output Jitter < 6fs_RMS
- (Integration BW = 12kHz to 20MHz, f = 4.5GHz)
Additive Output Jitter 65fs_RMS (ADC SNR Method)
EZSync^™, ParallelSync^™ Multichip Synchronization
–229dBc/Hz Normalized In-Band Phase Noise Floor
–281dBc/Hz Normalized In-Band 1/f Noise

Eleven Independent, Low Noise Outputs with Programmable Coarse Digital and Fine Analog Delays
Flexible Outputs Can Serve as Either a Device Clock or SYSREF Signal
Reference Input Frequency up to 500MHz
LTC6952Wizard^™ Software Design Tool Support
–40ºC to 125°C Operating Junction Temperature Range

Part details & applications

The LTC6952 is a high performance, ultralow jitter, JESD204B/C clock generation and distribution IC. It includes a Phase Locked Loop (PLL) core, consisting of a reference divider, phase-frequency detector (PFD) with a phase-lock indicator, ultralow noise charge pump and integer feedback divider. The LTC6952’s eleven outputs can be configured as up to five JESD204B/C subclass 1 device clock/SYSREF pairs plus one general purpose output, or simply eleven general purpose clock outputs for non-JESD204B/C applications. Each output has its own individually programmable frequency divider and output driver. All outputs can also be synchronized and set to precise phase alignment using individual coarse half-cycle digital delays and fine analog time delays.

For applications requiring more than eleven total outputs, multiple LTC6952s can be connected together using the EZSync or ParallelSync synchronization protocols.

Applications

High Performance Data Converter Clocking
Wireless Infrastructure
Test and Measurement

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