ADFS7124-4

RECOMMENDED FOR NEW DESIGNS

4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference

Analog Devices ADFS7124-4 Product Info

10 February 2026 4

Features

Functional safety approved to SC3 by TÜV Rheinland, File Number 968/FSP 2188.01/23
Three power modes
RMS noise
- Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 μA typical)
- Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 μA typical)
- Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 μA typical)
Up to 22 noise free bits in all power modes (gain = 1)
Output data rate
- Full power: 9.38 SPS to 19,200 SPS
- Mid power: 2.34 SPS to 4800 SPS
- Low power: 1.17 SPS to 2400 SPS
Rail-to-rail analog inputs for gains > 1
Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle settling)
Diagnostic functions (which aid safe integrity level (SIL) certification)
Crosspoint multiplexed analog inputs
- 4 differential/7 pseudodifferential inputs

Programmable gain (1 to 128)
Band gap reference with 15 ppm/°C drift maximum (70 μA)
Matched programmable excitation currents
Internal clock oscillator
On-chip bias voltage generator
Low-side power switch
General-purpose outputs
Multiple filter options
Internal temperature sensor
Self and system calibration
Sensor burnout detection
Automatic channel sequencer
Per channel configuration
Power supply: 2.7 V to 3.6 V and ±1.8 V
Independent interface power supply
Power-down cur

Part details & applications

The ADFS7124-4 is a low power, low noise, completely integrated analog front end for high precision measurement applications. The device contains a low noise, 24-bit Σ-Δ analog-to-digital converter (ADC), and can be configured to have four differential inputs or seven single-ended or pseudo differential inputs. The on-chip low gain stage ensures that signals of small amplitude can be interfaced directly to the ADC.

One of the major advantages of the ADFS7124-4 is that it gives the flexibility to employ one of three integrated power modes. The current consumption, range of output data rates, and RMS noise can be tailored with the power mode selected. The device also offers a multitude of filter options, ensuring the highest degree of flexibility.

The ADFS7124-4 can achieve simultaneous 50 Hz and 60 Hz rejection when operating at an output data rate of 25 SPS (single cycle settling), with rejection in excess of 80 dB achieved at lower output data rates.

The ADFS7124-4 establishes the highest degree of signal chain integration. The device contains a precision, low noise, low drift internal band gap reference, and also accepts an external differential reference, which can be internally buffered. Other key integrated features include programmable low drift excitation current sources, burnout currents, and a bias voltage generator, which sets the common-mode voltage of a channel to (AV_DD-AV_SS)/2. The low-side power switch enables the user to power down bridge sensors between conversions, ensuring the absolute minimal power consumption of the system. The device also allows the option of operating with either an internal or external clock.

The integrated channel sequencer allows several channels to be enabled simultaneously, and the ADFS7124-4 sequentially converts on each enabled channel, simplifying communication with the device. As many as 16 channels can be enabled at any t

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