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The ADAR3002 is a 17.7 GHz to 21.2 GHz receive, 2-beam and 4-dual polarized elements, beamforming chip for polarized phased arrays. Each of the 16 RF paths provides a ≥31 dB gain adjustment range and 360 degree phase adjustment, with resolution of less than ≤0.5 dB and 5.625 degrees, respectively, through variable amplitude and phase (VAP) blocks. Each VAP contains a digital stepped attenuator (DSA) and phase shifter unit (PSU).
Access to on-chip control registers and memory is through a simple 3-wire or 4-wire serial port interface (SPI). In addition, four address pins allow SPI control of up to 16 devices on the same serial lines. The random access memory (RAM) has storage for up to 256 beamstates, organized into 64 beamstates per polarization per beam. The sequencer selects and advances the beamstate being sourced from either the RAM or the FIFO.
ADAR3002 is available in a 176-ball 6.6 x 6.6 mm Wafer Level Chip Scale Package (WLCSP) and is specified from −40°C to +85°C.
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