Analog Devices AD9689 Product Info

• JESD204B (Subclass 1) coded serial digital outputs
  • Support for lane rates up to 16 Gbps per lane
• Noise density
  • −152 dBFS/Hz at 2.56 GSPS at full-scale voltage = 1.7 V p-p
  • −154 dBFS/Hz at 2.56 GSPS at full-scale voltage = 2.0 V p-p
  • −154.2 dBFS/Hz at 2.0 GSPS at full-scale voltage = 1.7 V p-p
  • −155.3 dBFS/Hz at 2.0 GSPS at full-scale voltage = 2.0 V p-p
• 1.55 W total power per channel at 2.56 GSPS (default settings)
• SFDR at 2.56 GSPS encode
  • 73 dBFS at 1.8 GHz A_IN at −2.0 dBFS
  • 59 dBFS at 5.53 GHz A_IN at −2.0 dBFS
    • full-scale voltage = 1.1 V p-p
• SNR at 2.56 GSPS encode
  • 59.7 dBFS at 1.8 GHz A_IN at −2.0 dBFS
  • 53.0 dBFS at 5.53 GHz A_IN at −2.0 dBFS
    • full-scale voltage = 1.1 V p-p
• SFDR at 2.0 GSPS encode
  • 78 dBFS at 900 MHz A_IN at −2.0 dBFS
  • 62 dBFS at 5.53 GHz A_IN at −2.0 dBFS
    • full-scale voltage = 1.1 V p-p
• SNR at 2.0 GSPS encode
  • 62.7 dBFS at 900 MHz A_IN at −2.0 dBFS
  • 53.1 dBFS at 5.5 GHz A_IN at −2.0 dBFS
    • full-scale voltage = 1.1 V p-p
• 0.975 V, 1.9 V, and 2.5 V dc supply operation
• 9 GHz analog input full power bandwidth (−3 dB)
• Amplitude detect bits for efficient AGC implementation
• Programmable FIR filters for analog channel loss equalization
• 2 inte

The AD9689 is a dual, 14-bit, 2.0 GSPS/2.6 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 5 GHz. The −3 dB bandwidth of the ADC input is 9 GHz. The AD9689 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.

The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of multiple cascaded signal processing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and decimation rates. The NCO has the option to select preset bands over the general-purpose input/output (GPIO) pins, which enables the selection of up to three bands. Operation of the AD9689 between the DDC modes is selectable via SPI-programmable profiles.

In addition to the DDC blocks, the AD9689 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs,