AD9094

RECOMMENDED FOR NEW DESIGNS

8-Bit, 1 GSPS, JESD204B, Quad Analog-to-Digital Converter

Analog Devices AD9094 Product Info

10 February 2026 4

Features

JESD204B (Subclass 1 and Subclass 0) coded serial digital outputs
- Lane rates up to 15 Gbps
1.6 W total power at 1 GSPS
- 400 mW per ADC channel
SFDR: 71 dBFS at 611 MHz (1.44 V p-p input range)
SNR: 48.6 dBFS at 611 MHz (1.44 V p-p input range)
SINAD: 48.5 dBFS at 611 MHz (1.44 V p-p input range)
0.9 V, 1.8 V, and 2.5 V dc supply operation
No missing codes

Internal ADC voltage reference
Analog input buffer
On-chip dithering to improve small signal linearity
Flexible differential input range
- 1.44 V p-p to 2.16 V p-p (1.44 V p-p default)
1.4 GHz analog input full power bandwidth
Fast detect bits for efficient AGC implementation
Differential clock input
Integer clock divide by 1, 2, 4, or 8
On-chip temperature diode
Flexible JESD204B lane configurations

Part details & applications

The AD9094 is an 8-bit, 1 GSPS, quad analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. The device is designed to sample wide bandwidth analog signals up to 1.4 GHz. The AD9094 is optimized for wide input bandwidth, a high sampling rate, high works linearity, and low power in a small package.

The quad-ADC cores feature multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs that support a variety of user-selectable input ranges. An integrated voltage reference facilitates design considerations. The analog inputs and clock signals are differential inputs.

Users can configure each pair of intermediate frequency (IF) receiver outputs onto either one or two lanes of JESD204B Subclass 1 or Subclass 0, high speed, serialized outputs, depending on the sample rate and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF±, SYNCINB±AB, and SYNCINB±CD input pins.

The AD9094 has flexible power-down options that allow significant power savings when desired. To program the power down options, use the 1.8 V capable, serial port interface (SPI).

The AD9094 is available in a Pb-free, 72-lead, lead frame chip scale package (LFCSP) and is specified over a junction temperature range of −40°C to +105°C. This product may be protected by one or more U.S. or international patents.

Note that throughout the data sheet, multifunction pins, such as PDWN/STBY, are referred to either by the entire pin name or by a single function of the pin, for example, PDWN, when only that function is relevant.

Product Highlights

Low power consumption per channel.
JESD204B lane rate support up to 15 Gbps.
Wide, full

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