Analog Devices AD6688 Product Info

• JESD204B (Subclass 1) coded serial digital outputs
  
  • Support for lane rates up to 16 Gbps per lane
• 1.7 W total power per channel at 3 GSPS (default settings)
• Performance at −2 dBFS amplitude, 2.6 GHz input
  
  • SFDR = 70 dBFS
  • NSD = −148.0 dBFS/Hz
• Performance at −9 dBFS amplitude, 2.6 GHz input
  
  • SFDR = 75 dBFS
  • NSD = −151.4 dBFS/Hz
• Integrated input buffer
• Noise density = −152.0 dBFS/Hz
• 0.975 V, 1.9 V, and 2.5 V dc supply operation
• 9 GHz analog input full power bandwidth (−3 dB)
• Amplitude detect bits for efficient AGC implementation
• Two Integrated wideband digital processors per channel
  
  • 48-bit NCO
  • 4 cascaded half band filters
• Phase coherent NCO switching
  
  • Up to 4 channels available
• Serial port control
  
  • Integer clock divide by 2 and divide by 4
  • Flexible JESD204B lane configurations
• On-chip dither

The AD6688 is a 1.2 GHz bandwidth, mixed-signal, direct radio frequency (RF) sampling receiver. It consists of two 14-bit, 3.0 GSPS analog-to-digital converters (ADCs) and various digital signal processing blocks consisting of four wideband digital downconverters (DDCs). The AD6688 has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 5 GHz. The 3 dB bandwidth of the ADC input is greater than 9 GHz. The AD6688 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.

The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four DDCs through a crossbar mux. Each DDC consists of up to five cascaded signal processing stages: a 48-bit numerically controlled oscillator (NCO) and up to four half-band decimation filters. The NCO has the option to select preset bands over the general-purpose input/output (GPIO) pins, which enables selection of up to three bands. Operation of the AD6688 between the DDC modes is selectable via SPI-programmable profiles.

In addition to the DDC blocks, the AD6688 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this t