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AD6642
  • AD6642
  • AD6642

AD6642

PRODUCTION

Dual IF Receiver

Analog Devices AD6642 Product Info

10 February 2026 6

Features

  • 11-bit, 200 MSPS output data rate per channel
  • Integrated noise shaping requantizer (NSR)
  • Performance with NSR enabled
    SNR: 75.5 dBFS in 40 MHz band to 70 MHz @ 185 MSPS
    SNR: 73.7 dBFS in 60 MHz band to 70 MHz @ 185 MSPS
  • Performance with NSR disabled
    SNR: 66.5 dBFS to 70 MHz @ 185 MSPS
    SFDR: 83 dBc to 70 MHz @ 185 MSPS
  • Low power: 0.62 W @ 185 MSPS
  • 1.8 V analog supply operation
  • 1.8 V LVDS (ANSI-644 levels) output
  • 1-to-8 integer clock divider
  • Internal ADC voltage reference
  • 1.75 V p-p analog input range
    (programmable to 2.0 Vp-p)
  • Differential analog inputs with 800 MHz bandwidth
  • See data sheet for additional features

Part details & applications

The AD6642 is an 11-bit, 200 MSPS, dual-channel intermediate frequency (IF) receiver specifically designed to support multi-antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired.

The device consists of two high performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features a wide bandwidth switched-capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) compensates for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows for improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the external MODE pin or the SPI.

With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6642 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining an 11-bit output resolution. The NSR block can be programmed to provide a bandwidth of either 22% or 33% of the sample clock. For example, with a sample clock rate of 185 MSPS, the AD6642 can achieve up to 75.5 dBFS SNR for a 40 MHz bandwidth in the 22% mode and up to 73.7 dBFS SNR for a 60 MHz bandwidth in the 33% mode.

With the NSR block disabled, the ADC data is provided directly to the output with a resolution of 11 bits. The AD6642 can achieve up to 66.5 dBFS SNR for the entire Nyquist bandwidth when operated in this mode. This allows the AD6642 to be used in telecommunication applications such as a digital predist

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