AD4032-24

RECOMMENDED FOR NEW DESIGNS

24-Bit, 500 kSPS, SAR ADC

Analog Devices AD4032-24 Product Info

10 February 2026 9

Features

High performance
- Throughput: 2 MSPS (AD4030-24) or 500 kSPS (AD4032-24) options
- INL: ±0.9 ppm maximum from −40°C to +125°C
- SNR: 108.4 dB typical
- THD: −127 dB typical
- NSD: −169 dBFS/Hz typical
Low power
- 30 mW at 2 MSPS
- 10 mW at 500 kSPS
- 3 mW at 10 kSPS
Easy Drive^™ features reduce system complexity
- Low 1.2 μA input current for dc inputs
- Wide input common-mode range: −(1/128) × V_REF to +(129/128) × V_REF

Flexible external reference voltage range: 4.096 V to 5 V
- Accurate integrated reference buffer with 2 μF bypass capacitor
Programmable block averaging filter with up to 2¹⁶ decimation
- Extended sample resolution to 30 bits
- Overrange and synchronization bits
Flexi-SPI digital interface
- 1, 2, or 4 SDO lanes allows slower SCK
- Echo clock mode simplifies use of digital isolator
- Compatible with 1.2 V to 1.8 V logic
7 mm × 7 mm 64-Ball CSP_BGA package with internal supply and reference capacitors to help reduce system footprint

Part details & applications

The AD4030-24/AD4032-24 are 2 MSPS or 500 kSPS successive approximation register (SAR), analog-to-digital converters (ADC) with Easy Drive^™. With a guaranteed maximum ±0.9 ppm integral nonlinearity (INL) and no missing codes at 24-bits, the AD4030-24/AD4032-24 achieve unparalleled precision from −40°C to +125°C. Figure 1 shows the functional architecture of the AD4030-24/AD4032-24.

A low drift, internal precision reference buffer eases voltage reference sharing with other system circuitry. The AD4030-24/AD4032-24 offer a typical dynamic range of 109 dB when using a 5 V reference. The low noise floor enables signal chains requiring less gain and lower power. A block averaging filter with programmable decimation ratio can increase dynamic range up to 155.5 dB. The wide differential input and common mode ranges allow inputs to use the full ±V_REF range without saturating, simplifying signal conditioning requirements and system calibration. The improved settling of the Easy Drive analog inputs broadens the selection of analog front-end components compatible with the AD4030-24/AD4032-24. Both single-ended and differential signals are supported.

The versatile Flexi-SPI serial peripheral interface (SPI) eases host processor and ADC integration. A wide data clocking window, multiple SDO lanes, and optional dual data rate (DDR) data clocking can reduce the serial clock to 10 MHz while operating at a sample rate of 2 MSPS or 500 kSPS. Echo clock mode and ADC host clock mode relax the timing requirements and simplify the use of digital isolators.

The 7 mm × 7 mm, 64-Ball CSP_BGA package of the AD4030-24/AD4032-24 integrates all critical power supply and reference bypass capacitors, reducing the footprint and system component count, and lessening sensitivity to board layout.

APPLICATIONS

Automatic test equip

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