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TPS53685
  • TPS53685
  • TPS53685

TPS53685

ACTIVE

Eight-phase digital step-down multiphase controller with SVI3 and PMBus for AMD platform

Texas Instruments TPS53685 Product Info

1 April 2026 1

Parameters

Rating

Catalog

Topology

Multiphase

Iout (max) (A)

765

Vin (max) (V)

17

Vin (min) (V)

4.5

Vout (max) (V)

5.5

Vout (min) (V)

0.25

Control mode

D-CAP+

Features

Adjustable current limit, Dynamic Voltage Scaling, Enable, Light Load Efficiency, Multiple Outputs, Output discharge, PMBus, Phase Interleaving, Power good, Pre-Bias Start-Up, Remote Sense, Synchronous Rectification, UVLO adjustable, Voltage Margining

Iq (typ) (A)

0.06

Number of phases

8

Operating temperature range (°C)

-40 to 105

Package

WQFN (RSB)-40-25 mm² 5 x 5

Features

  • Input voltage range: 4.5 V to 17 V
  • Output voltage range: 0.25 V to 5.5 V
  • Dual output supporting N+M ≤ 8 phases, M ≤ 4 phases
  • Native trans-inductor voltage regulator (TLVR) topology support
  • AMD SVI3 compliant
  • Enhanced D-CAP+™ control to provide superior transient performance with excellent dynamic current sharing
  • Programmable loop compensations
  • Flexible phase-firing sequencing
  • Individual phase current calibrations and reports
  • Dynamic phase shedding with programmable current threshold for optimizing efficiency at light and heavy loads
  • Fast phase-adding for undershoot reduction
  • Driverless configuration for efficient high-frequency switching
  • Fully compatible with TI NexFET™ power stages for high-density solutions
  • Accurate, adjustable voltage positioning
  • Patented AutoBalance™ phase current balancing
  • Selectable per-phase current limit
  • PMBus™ system interface for telemetry of voltage, current, power, temperature, and fault conditions
  • 5.00 × 5.00 mm, 40-pin, 0.4 mm pitch, QFN package
  • Input voltage range: 4.5 V to 17 V
  • Output voltage range: 0.25 V to 5.5 V
  • Dual output supporting N+M ≤ 8 phases, M ≤ 4 phases
  • Native trans-inductor voltage regulator (TLVR) topology support
  • AMD SVI3 compliant
  • Enhanced D-CAP+™ control to provide superior transient performance with excellent dynamic current sharing
  • Programmable loop compensations
  • Flexible phase-firing sequencing
  • Individual phase current calibrations and reports
  • Dynamic phase shedding with programmable current threshold for optimizing efficiency at light and heavy loads
  • Fast phase-adding for undershoot reduction
  • Driverless configuration for efficient high-frequency switching
  • Fully compatible with TI NexFET™ power stages for high-density solutions
  • Accurate, adjustable voltage positioning
  • Patented AutoBalance™ phase current balancing
  • Selectable per-phase current limit
  • PMBus™ system interface for telemetry of voltage, current, power, temperature, and fault conditions
  • 5.00 × 5.00 mm, 40-pin, 0.4 mm pitch, QFN package

Description

The TPS53685 is a fully AMD SVI3 compliant step-down controller with trans-inductor voltage regulator (TLVR) topology support, dual channels, built-in non-volatile memory (NVM), PMBus™ interface, and full compatible with TI NexFET™ smart power stages. Advanced control features such as D-CAP+™ architecture with undershoot reduction (USR) provide fast transient response and good current sharing, minimizing output capacitance requirements. The device also provides a novel phase interleaving strategy and dynamic phase shedding for efficiency improvements at different loads. Adjustable control of VCORE slew rate and voltage positioning work with the AMD SVI3 features. In addition, the device supports the PMBus communication interface for reporting the telemetry of voltage, current, power, temperature, and fault conditions to the systems. All programmable parameters can be configured by the PMBus interface and can be stored in NVM as the new default values to minimize the external component count.

The TPS53685 device is offered in a thermally enhanced 40-pin QFN packaged and is rated to operate from –40°C to 125°C.

The TPS53685 is a fully AMD SVI3 compliant step-down controller with trans-inductor voltage regulator (TLVR) topology support, dual channels, built-in non-volatile memory (NVM), PMBus™ interface, and full compatible with TI NexFET™ smart power stages. Advanced control features such as D-CAP+™ architecture with undershoot reduction (USR) provide fast transient response and good current sharing, minimizing output capacitance requirements. The device also provides a novel phase interleaving strategy and dynamic phase shedding for efficiency improvements at different loads. Adjustable control of VCORE slew rate and voltage positioning work with the AMD SVI3 features. In addition, the device supports the PMBus communication interface for reporting the telemetry of voltage, current, power, temperature, and fault conditions to the systems. All programmable parameters can be configured by the PMBus interface and can be stored in NVM as the new default values to minimize the external component count.

The TPS53685 device is offered in a thermally enhanced 40-pin QFN packaged and is rated to operate from –40°C to 125°C.

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