- Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
- 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
- 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
- Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
- Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
- Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
- Data Bus With a Bus Holder Feature
- Extended Addressing Mode for 8M × 16-Bit Maximum Addressable External Program Space
- 64K x 16-Bit On-Chip RAM Composed of:
- Eight Blocks of 8K × 16-Bit On-Chip Dual-Access Program/Data RAM
- 16K × 16-Bit On-Chip ROM Configured for Program Memory
- Enhanced External Parallel Interface (XIO2)
- Single-Instruction-Repeat and Block-Repeat Operations for Program Code
- Block-Memory-Move Instructions for Better Program and Data Management
- Instructions With a 32-Bit Long Word Operand
- Instructions With Two- or Three-Operand Reads
- Arithmetic Instructions With Parallel Store and Parallel Load
- Conditional Store Instructions
- Fast Return From Interrupt
- On-Chip Peripherals
- Software-Programmable Wait-State Generator and Programmable Bank-Switching
- On-Chip Programmable Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source (1)
- One 16-Bit Timer
- Six-Channel Direct Memory Access (DMA) Controller
- Three Multichannel Buffered Serial Ports (McBSPs)
- 8/16-Bit Enhanced Parallel Host-Port Interface (HPI8/16)
- Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
- CLKOUT Off Control to Disable CLKOUT
- On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (2) (JTAG) Boundary Scan Logic
- 144-Pin Ball Grid Array (BGA) (GGU Suffix)
- 144-Pin Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
- 6.25-ns Single-Cycle Fixed-Point Instruction Execution Time (160 MIPS)
- 8.33-ns Single-Cycle Fixed-Point Instruction Execution Time (120 MIPS)
- 3.3-V I/O Supply Voltage (160 and 120 MIPS)
- 1.6-V Core Supply Voltage (160 MIPS)
- 1.5-V Core Supply Voltage (120 MIPS)
(1) The on-chip oscillator is not available on all 5410A devices. For applicable devices, see the TMS320VC5410A Digital Signal Processor Silicon Errata (literature number SPRZ187).
(2) IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
NOTE: This data manual is designed to be used in conjunction with the TMS320C54x™ DSP Functional Overview (literature number SPRU307).
TMS320C54x, MicroStar BGA, TMS320C54x, C54x, TMS320C5000, C5000, TMS320 are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
- Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
- 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
- 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
- Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
- Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
- Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
- Data Bus With a Bus Holder Feature
- Extended Addressing Mode for 8M × 16-Bit Maximum Addressable External Program Space
- 64K x 16-Bit On-Chip RAM Composed of:
- Eight Blocks of 8K × 16-Bit On-Chip Dual-Access Program/Data RAM
- 16K × 16-Bit On-Chip ROM Configured for Program Memory
- Enhanced External Parallel Interface (XIO2)
- Single-Instruction-Repeat and Block-Repeat Operations for Program Code
- Block-Memory-Move Instructions for Better Program and Data Management
- Instructions With a 32-Bit Long Word Operand
- Instructions With Two- or Three-Operand Reads
- Arithmetic Instructions With Parallel Store and Parallel Load
- Conditional Store Instructions
- Fast Return From Interrupt
- On-Chip Peripherals
- Software-Programmable Wait-State Generator and Programmable Bank-Switching
- On-Chip Programmable Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source (1)
- One 16-Bit Timer
- Six-Channel Direct Memory Access (DMA) Controller
- Three Multichannel Buffered Serial Ports (McBSPs)
- 8/16-Bit Enhanced Parallel Host-Port Interface (HPI8/16)
- Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
- CLKOUT Off Control to Disable CLKOUT
- On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (2) (JTAG) Boundary Scan Logic
- 144-Pin Ball Grid Array (BGA) (GGU Suffix)
- 144-Pin Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
- 6.25-ns Single-Cycle Fixed-Point Instruction Execution Time (160 MIPS)
- 8.33-ns Single-Cycle Fixed-Point Instruction Execution Time (120 MIPS)
- 3.3-V I/O Supply Voltage (160 and 120 MIPS)
- 1.6-V Core Supply Voltage (160 MIPS)
- 1.5-V Core Supply Voltage (120 MIPS)
(1) The on-chip oscillator is not available on all 5410A devices. For applicable devices, see the TMS320VC5410A Digital Signal Processor Silicon Errata (literature number SPRZ187).
(2) IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
NOTE: This data manual is designed to be used in conjunction with the TMS320C54x™ DSP Functional Overview (literature number SPRU307).
TMS320C54x, MicroStar BGA, TMS320C54x, C54x, TMS320C5000, C5000, TMS320 are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
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