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SN74LVC1G80-Q1
  • SN74LVC1G80-Q1
  • SN74LVC1G80-Q1

SN74LVC1G80-Q1

ACTIVE

Automotive Single Positive-Edge-Triggered D-Type Flip-Flop

Texas Instruments SN74LVC1G80-Q1 Product Info

1 April 2026 1

Parameters

Number of channels

1

Technology family

LVC

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

5.5

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

150

IOL (max) (mA)

32

IOH (max) (mA)

-32

Supply current (max) (µA)

10

Features

Balanced outputs, Over-voltage tolerant inputs

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Package

SOT-SC70 (DCK)-5-4.2 mm² 2 x 2.1

Features

  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • ±4000-V Human-Body Model (HBM) ESD Classification Level 3A
    • ±1000-V Charged-Device Model (CDM) ESD Classification Level C5
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Supports Down Translation to VCC
  • Maximum tpd of 6 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff supports Partial-Power-Down Mode and Back-Drive Protection
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • ±4000-V Human-Body Model (HBM) ESD Classification Level 3A
    • ±1000-V Charged-Device Model (CDM) ESD Classification Level C5
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Supports Down Translation to VCC
  • Maximum tpd of 6 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff supports Partial-Power-Down Mode and Back-Drive Protection

Description

The SN74LVC1G80-Q1 device is an automotive AEC-Q100 qualified, single positive-edge-triggered D-type flip-flop that is designed for 1.65-V to 5.5-V VCC operation.

When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

The SN74LVC1G80-Q1 device is an automotive AEC-Q100 qualified, single positive-edge-triggered D-type flip-flop that is designed for 1.65-V to 5.5-V VCC operation.

When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

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