Texas Instruments SN74AUP1G80 Product Info

Parameters

Number of channels	1
Technology family	AUP
Supply voltage (min) (V)	0.8
Supply voltage (max) (V)	3.6
Input type	Standard CMOS
Output type	Push-Pull
Clock frequency (max) (MHz)	260
IOL (max) (mA)	4
IOH (max) (mA)	-4
Supply current (max) (µA)	0.9
Features	Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)
Operating temperature range (°C)	-40 to 85
Rating	Catalog

Package

DSBGA (YFP)-6-1.4000000000000001 mm² 1 x 1.4000000000000001

Features

Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
  (A114-B, Class II)
- 1000-V Charged-Device Model (C101)
Available in the Texas Instruments NanoStar™ Package
Low Static-Power Consumption
(I_CC = 0.9 µA Maximum)
Low Dynamic-Power Consumption
(C_pd = 4.3 pF Typical at 3.3 V)
Low Input Capacitance (C_i = 1.5 pF Typical)
Low Noise – Overshoot and Undershoot <10% of V_CC
I_off Supports Partial-Power-Down Mode Operation
Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input
(V_hys = 250 mV Typical at 3.3 V)
Wide Operating V_CC Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
t_pd = 4.4 ns Maximum at 3.3 V
Suitable for Point-to-Point Applications

Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
  (A114-B, Class II)
- 1000-V Charged-Device Model (C101)
Available in the Texas Instruments NanoStar™ Package
Low Static-Power Consumption
(I_CC = 0.9 µA Maximum)
Low Dynamic-Power Consumption
(C_pd = 4.3 pF Typical at 3.3 V)
Low Input Capacitance (C_i = 1.5 pF Typical)
Low Noise – Overshoot and Undershoot <10% of V_CC
I_off Supports Partial-Power-Down Mode Operation
Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input
(V_hys = 250 mV Typical at 3.3 V)
Wide Operating V_CC Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
t_pd = 4.4 ns Maximum at 3.3 V
Suitable for Point-to-Point Applications

Description

The AUP family is TIs premier solution to the industrys low-power needs in battery-powered portable applications. This family assures a low static- and dynamic-power consumption across the entire V_CC range of 0.8 V to 3.6 V, resulting in increased battery life (see AUP – The Lowest-Power Family). This product also maintains excellent signal integrity (see Excellent Signal Integrity).

This is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

The AUP family is TIs premier solution to the industrys low-power needs in battery-powered portable applications. This family assures a low static- and dynamic-power consumption across the entire V_CC range of 0.8 V to 3.6 V, resulting in increased battery life (see AUP – The Lowest-Power Family). This product also maintains excellent signal integrity (see Excellent Signal Integrity).

This is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

ELECTRONIC COMPONENTS
All In One Distributor

SN74AUP1G80

Low-Power Single Postitive-Edge-Triggered D-Type Flip-Flop

Texas Instruments SN74AUP1G80 Product Info

Parameters

Package

Features

Description

SUBMITTED SUCCESSFULLY！

ELECTRONIC COMPONENTS All In One Distributor

SN74AUP1G80

Low-Power Single Postitive-Edge-Triggered D-Type Flip-Flop

Texas Instruments SN74AUP1G80 Product Info

Parameters

Package

Features

Description

SUBMITTED SUCCESSFULLY！

ELECTRONIC COMPONENTS
All In One Distributor