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SN74ALVC16835
  • SN74ALVC16835
  • SN74ALVC16835

SN74ALVC16835

ACTIVE

18-Bit Universal Bus Driver With 3-State Outputs

Texas Instruments SN74ALVC16835 Product Info

1 April 2026 0

Parameters

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

3.6

Number of channels

18

IOL (max) (mA)

24

IOH (max) (mA)

-32

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Ultra high speed (tpd <5ns)

Technology family

ALVC

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Package

SSOP (DL)-56-190.647 mm² 18.42 x 10.35

Features

  • Member of the Texas Instruments Widebus™ Family
  • Operates From 1.65 V to 3.6 V
  • Max tpd of 2 ns at 3.3 V
  • ±24-mA Output Drive at 3.3 V
  • Ideal for Use in PC100 Register DIMM Revision 1.1
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.

  • Member of the Texas Instruments Widebus™ Family
  • Operates From 1.65 V to 3.6 V
  • Max tpd of 2 ns at 3.3 V
  • ±24-mA Output Drive at 3.3 V
  • Ideal for Use in PC100 Register DIMM Revision 1.1
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.

Description

This 18-bit universal bus driver is designed for 1.65-V to 3.6-V VCC operation.

Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This 18-bit universal bus driver is designed for 1.65-V to 3.6-V VCC operation.

Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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