0
ACTIVE
PGA/VGA |
PGA |
Number of channels |
10 |
Vs (min) (V) |
2.2 |
Vs (max) (V) |
5.5 |
Input type |
Single-ended |
Output type |
Single-ended |
Input offset drift (±) (typ) (µV/°C) |
0.6 |
Interface type |
SPI |
Noise at 1 kHz (typ) (V√Hz) |
0.000000013 |
BW at Acl (MHz) |
10 |
Acl, min spec gain (V/V) |
1 |
Gain (max) (dB) |
42 |
Architecture |
CMOS |
Features |
Binary gains, Daisy chain, Shutdown |
Vos (offset voltage at 25°C) (typ) (mV) |
0.025 |
Input voltage noise (typ) (µV√Hz) |
0.012 |
Slew rate (typ) (V/µs) |
3 |
Iq per channel (typ) (mA) |
1.08 |
Gain error (typ) (%) |
0.006 |
Gain drift (max) (ppm/°C) |
0.5 |
Rating |
Catalog |
Operating temperature range (°C) |
-40 to 125 |
TSSOP (PW)-20-41.6 mm² 6.5 x 6.4
The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in a 10-pin, VSSOP package. The PGA116 and PGA117 (binary and scope gains) offer 10 analog inputs, a SPI interface with daisy-chain capability, and hardware and software shutdown in a 20-pin TSSOP package.
All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200.
WELL LINK CHIPS GROUP CO.,LIMITED FLAT/RM 1802 BEVERLY HOUSE 93-107 LOCKHART ROAD WANCHAI HK
