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DS90UA102-Q1
  • DS90UA102-Q1
  • DS90UA102-Q1

DS90UA102-Q1

ACTIVE

Multi-Channel Digital Audio Deserializer

Texas Instruments DS90UA102-Q1 Product Info

1 April 2026 0

Parameters

Applications

In-vehicle Infotainment (IVI)

Input compatibility

FPD-Link III LVDS

Function

Deserializer

Output compatibility

LVCMOS

Color depth (bpp)

8

Features

Low-EMI Point-to-Point Communication

EMI reduction

LVDS

Diagnostics

BIST

Rating

Automotive

Operating temperature range (°C)

-40 to 105

Package

WQFN (RHS)-48-49 mm² 7 x 7

Features

  • Digital Audio Deserializer
  • Flexible Digital Audio Outputs, supporting I2S
    (Stereo) and TDM (Multi-Channel) Formats
  • Coaxial or Single Differential Pair Interconnect
  • High Speed Serial Input Interface
  • Very Low Latency (<15 µs)
  • Bidirectional Control Interface Channel with I2C
    Compatible Serial Control Bus
  • Supports up to 8 Stereo I2S or TDM Audio Outputs
  • Supports Audio System Clocks from 10 MHz to 50 MHz
  • Single 1.8V Supply
  • 1.8V or 3.3V I/O Interface
  • 4/4 Dedicated General Purpose Inputs/Outputs
  • AC-Coupled STP or Coaxial Cable up to 15m
  • DC-Balanced & Scrambled Data w/ Embedded Clock
  • Adaptive Cable Equalization
  • At-Speed Link BIST Mode and LOCK Status Pin
  • Automotive Grade Product: AEC-Q100 Grade 2 Qualified
  • Temperature Range: –40°C to 105°C
  • ISO 10605 and IEC 61000-4-2 ESD Compliant
  • Digital Audio Deserializer
  • Flexible Digital Audio Outputs, supporting I2S
    (Stereo) and TDM (Multi-Channel) Formats
  • Coaxial or Single Differential Pair Interconnect
  • High Speed Serial Input Interface
  • Very Low Latency (<15 µs)
  • Bidirectional Control Interface Channel with I2C
    Compatible Serial Control Bus
  • Supports up to 8 Stereo I2S or TDM Audio Outputs
  • Supports Audio System Clocks from 10 MHz to 50 MHz
  • Single 1.8V Supply
  • 1.8V or 3.3V I/O Interface
  • 4/4 Dedicated General Purpose Inputs/Outputs
  • AC-Coupled STP or Coaxial Cable up to 15m
  • DC-Balanced & Scrambled Data w/ Embedded Clock
  • Adaptive Cable Equalization
  • At-Speed Link BIST Mode and LOCK Status Pin
  • Automotive Grade Product: AEC-Q100 Grade 2 Qualified
  • Temperature Range: –40°C to 105°C
  • ISO 10605 and IEC 61000-4-2 ESD Compliant

Description

The DS90UA102-Q1 Deserializer, in conjunction with the DS90UA101-Q1 Serializer, provides a solution for distribution of digital audio in multi-channel audio systems. It receives a high-speed serialized interface with an embedded clock over a single shielded twisted pair or coaxial cable. The serial bus scheme supports high speed forward data transmission and low speed bidirectional control channel over the link. Consolidation of digital audio, general-purpose IO, and control signals over a single differential pair reduces the interconnect size and weight, while also reducing design challenges related to skew and system latency.

The DS90UA102-Q1 Deserializer extracts the clock and level shifts the signals from high-speed low voltage differential signaling to single-ended LVCMOS. The device outputs up to eight digital audio data channels, word/frame sync, bit clock, and system clock.

Four dedicated general purpose input pins and four general purpose output pins allow flexible implementation of control and interrupt signals to and from remote devices.

Adaptive equalization of the serial input stream provides compensation for transmission medium losses of the cable and reduces medium-induced deterministic jitter.

The DS90UA102-Q1 Deserializer, in conjunction with the DS90UA101-Q1 Serializer, provides a solution for distribution of digital audio in multi-channel audio systems. It receives a high-speed serialized interface with an embedded clock over a single shielded twisted pair or coaxial cable. The serial bus scheme supports high speed forward data transmission and low speed bidirectional control channel over the link. Consolidation of digital audio, general-purpose IO, and control signals over a single differential pair reduces the interconnect size and weight, while also reducing design challenges related to skew and system latency.

The DS90UA102-Q1 Deserializer extracts the clock and level shifts the signals from high-speed low voltage differential signaling to single-ended LVCMOS. The device outputs up to eight digital audio data channels, word/frame sync, bit clock, and system clock.

Four dedicated general purpose input pins and four general purpose output pins allow flexible implementation of control and interrupt signals to and from remote devices.

Adaptive equalization of the serial input stream provides compensation for transmission medium losses of the cable and reduces medium-induced deterministic jitter.

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