Product
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AFE5401-Q1
  • AFE5401-Q1
  • AFE5401-Q1

AFE5401-Q1

ACTIVE

Quad-Channel Integrated Analog Front End for Automotive Radar

Texas Instruments AFE5401-Q1 Product Info

1 April 2026 0

Parameters

Device type

Receiver

Number of input channels

4

Active supply current (typ) (mA)

1.5

Supply voltage (max) (V)

3.6

Operating temperature range (°C)

-40 to 105

Interface type

CMOS

Features

Low Power

Rating

Automotive

Package

VQFN (RGC)-64-81 mm² 9 x 9

Features

  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C4B
  • Integrated Analog Front-End Includes:
    • Quad LNA, Equalizer, PGA, Antialiasing Filter, and ADC
  • Input-Referred Noise with 30-dB PGA Gain:
    • 2.9-nV/√Hz for 15-dB LNA Gain
    • 2.0-nV/√Hz for 18-dB LNA Gain with HIGH_POW_LNA Mode
  • Simultaneous Sampling Across Channels
  • Programmable LNA Gain:
    12 dB, 15 dB, 16.5 dB, and 18 dB
  • Programmable Equalizer Modes
  • Built-In Diagnostic Modes
  • Temperature Sensor
  • Programmable-Gain Amplifiers (PGAs):
    • 0 dB to 30 dB in 3-dB Steps
  • Programmable, Third-Order, Antialiasing Filter:
    • 7 MHz, 8 MHz, 10.5 MHz, and 12 MHz
  • Analog-to-Digital Converter (ADC):
    • Quad Channel, 12 Bits, 25 MSPS per Channel
    • No External Decoupling Required for References
  • Parallel CMOS Outputs
  • 64-mW Total Core Power per Channel at
    25 MSPS per Channel
  • Supplies: 1.8 V and 3.3 V
  • Package: 9-mm × 9-mm VQFN-64
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C4B
  • Integrated Analog Front-End Includes:
    • Quad LNA, Equalizer, PGA, Antialiasing Filter, and ADC
  • Input-Referred Noise with 30-dB PGA Gain:
    • 2.9-nV/√Hz for 15-dB LNA Gain
    • 2.0-nV/√Hz for 18-dB LNA Gain with HIGH_POW_LNA Mode
  • Simultaneous Sampling Across Channels
  • Programmable LNA Gain:
    12 dB, 15 dB, 16.5 dB, and 18 dB
  • Programmable Equalizer Modes
  • Built-In Diagnostic Modes
  • Temperature Sensor
  • Programmable-Gain Amplifiers (PGAs):
    • 0 dB to 30 dB in 3-dB Steps
  • Programmable, Third-Order, Antialiasing Filter:
    • 7 MHz, 8 MHz, 10.5 MHz, and 12 MHz
  • Analog-to-Digital Converter (ADC):
    • Quad Channel, 12 Bits, 25 MSPS per Channel
    • No External Decoupling Required for References
  • Parallel CMOS Outputs
  • 64-mW Total Core Power per Channel at
    25 MSPS per Channel
  • Supplies: 1.8 V and 3.3 V
  • Package: 9-mm × 9-mm VQFN-64

Description

The AFE5401-Q1 is an analog front-end (AFE), targeting applications where the level of integration is critical. The device includes four channels, with each channel comprising a low-noise amplifier (LNA), a programmable equalizer (EQ), a programmable gain amplifier (PGA), and an antialias filter followed by a high-speed, 12-bit, analog-to-digital converter (ADC) at 25 MSPS per channel.

Each of the four differential input pairs are amplified by an LNA and are followed by a PGA with a programmable gain range from 0 dB to 30 dB. An antialias, low-pass filter (LPF) is also integrated between the PGA and ADC for each channel.

Each LNA, PGA, and antialiasing filter output is differential (limited to 2 VPP). The antialiasing filter drives the on-chip, 12-bit, 25-MSPS ADC. The four ADC outputs are multiplexed on a 12-bit, parallel, CMOS output bus.

The device is available in a 9-mm × 9-mm, VQFN-64 package and is specified over a temperature range of –40°C to +105°C. For more information, contact [email protected].

The AFE5401-Q1 is an analog front-end (AFE), targeting applications where the level of integration is critical. The device includes four channels, with each channel comprising a low-noise amplifier (LNA), a programmable equalizer (EQ), a programmable gain amplifier (PGA), and an antialias filter followed by a high-speed, 12-bit, analog-to-digital converter (ADC) at 25 MSPS per channel.

Each of the four differential input pairs are amplified by an LNA and are followed by a PGA with a programmable gain range from 0 dB to 30 dB. An antialias, low-pass filter (LPF) is also integrated between the PGA and ADC for each channel.

Each LNA, PGA, and antialiasing filter output is differential (limited to 2 VPP). The antialiasing filter drives the on-chip, 12-bit, 25-MSPS ADC. The four ADC outputs are multiplexed on a 12-bit, parallel, CMOS output bus.

The device is available in a 9-mm × 9-mm, VQFN-64 package and is specified over a temperature range of –40°C to +105°C. For more information, contact [email protected].

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