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ADS58J89
  • ADS58J89
  • ADS58J89

ADS58J89

ACTIVE

Quad 500MSPS Receiver and Feedback IC

Texas Instruments ADS58J89 Product Info

1 April 2026 4

Parameters

Number of input channels

4

Resolution (Bits)

14

Sample rate (max) (Msps)

500

Features

Decimating Filter, Differential Inputs, High Dynamic Range, Nap Mode, Out of Range Indicator, Power Down

Analog input BW (MHz)

900

Power consumption (typ) (mW)

3270

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Package

VQFN (RGC)-64-81 mm² 9 x 9

Features

  • 4-Ch, 14-Bit 500MSPS With Digital Signal Processing
  • Power Amplifier Linearization (Feedback) Modes
    • 14-Bits Every Other Sample at 250MSPS
    • Programmable Resolution vs Duty Cycle
      • Duty Cycle 3:2 (60% 11-Bit, 40% 9-Bit)
      • Duty Cycle 2:3 (40% 12-Bit, 60% 9-Bit)
      • Duty Cycle 1:3 (25% 14-Bit, 75% 9-Bit)
  • Traffic Receiver Modes
    • 14-Bit 250MSPS: Decimate by 2 Filter, High/Low Pass
    • 9-Bit SNR-Boost Filter (150-MHz Max Bandwidth)
    • 9-to-14-Bit TDD Burst (200-MHz Max Bandwidth)
  • Flexible Input Clock Buffer With Divide by 1/2/4
  • JESD204B Digital Interface up to 5.0Gbps
    • 1 or 2 Lanes per Channel, With Subclass 1
  • 64-Pin VQFN Package (9 × 9 mm)
  • 4-Ch, 14-Bit 500MSPS With Digital Signal Processing
  • Power Amplifier Linearization (Feedback) Modes
    • 14-Bits Every Other Sample at 250MSPS
    • Programmable Resolution vs Duty Cycle
      • Duty Cycle 3:2 (60% 11-Bit, 40% 9-Bit)
      • Duty Cycle 2:3 (40% 12-Bit, 60% 9-Bit)
      • Duty Cycle 1:3 (25% 14-Bit, 75% 9-Bit)
  • Traffic Receiver Modes
    • 14-Bit 250MSPS: Decimate by 2 Filter, High/Low Pass
    • 9-Bit SNR-Boost Filter (150-MHz Max Bandwidth)
    • 9-to-14-Bit TDD Burst (200-MHz Max Bandwidth)
  • Flexible Input Clock Buffer With Divide by 1/2/4
  • JESD204B Digital Interface up to 5.0Gbps
    • 1 or 2 Lanes per Channel, With Subclass 1
  • 64-Pin VQFN Package (9 × 9 mm)

Description

The ADS58J89 is a high-linearity, quad-channel, 14-bit, 250/500-MSPS IF (intermediate frequency) receiver. The four channels contain 500MSPS 14-bit ADCs followed by signal processing for wireless infrastructure systems. The channels can be configured in various modes depending on bandwidth, resolution and sample time requirements. The signal processing block contains selectable modes for decimation filters, SNR Boost filters, resolution versus time and time-division duplex (TDD) burst mode. Designed for high antenna count systems, the 4 channels provides high bandwidth and linearity to multi-channel receivers in a small footprint. The device can be dual function as traffic receiver and power amplifier linearization feedback path in TDD systems.

Key Specifications:

  • Power Dissipation: 875 mW/ch
  • Input Bandwidth (3dB): 900 MHz
  • Aperture Jitter: 98 fs rms
  • Channel Isolation: 85 dB
  • Performance at ∫in = 170 MHz at 1.25 Vpp,
    –1 dBFS
    • SNR: 65.8 dBFS
    • SFDR: 85 dBc HD2,3 95 dBFS non HD2,3

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