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ADC34J23
  • ADC34J23
  • ADC34J23

ADC34J23

ACTIVE

Quad-Channel, 12-Bit, 80-MSPS Analog-to-Digital Converter (ADC)

Texas Instruments ADC34J23 Product Info

1 April 2026 3

Parameters

Sample rate (max) (Msps)

80

Resolution (Bits)

12

Number of input channels

4

Interface type

JESD204B

Analog input BW (MHz)

450

Features

Low Power

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

584

Architecture

Pipeline

SNR (dB)

70.4

ENOB (Bits)

11.4

SFDR (dB)

95

Operating temperature range (°C)

-40 to 85

Input buffer

No

Package

VQFN (RGZ)-48-49 mm² 7 x 7

Features

  • Quad Channel
  • 12-Bit Resolution
  • Single 1.8-V Supply
  • Flexible Input Clock Buffer with Divide-by-1, -2, -4
  • SNR = 69.6 dBFS, SFDR = 86 dBc at
    fIN = 70 MHz
  • Ultra-Low Power Consumption:
    • 203 mW/Ch at 160 MSPS
  • Channel Isolation: 105 dB
  • Internal Dither
  • JESD204B Serial Interface:
    • Subclass 0, 1, 2 Compliant up to 3.2 Gbps
    • Supports One Lane per ADC up to 160 MSPS
  • Support for Multi-Chip Synchronization
  • Pin-to-Pin Compatible with 14-Bit Version
  • Package: VQFN-48 (7 mm × 7 mm)
  • Quad Channel
  • 12-Bit Resolution
  • Single 1.8-V Supply
  • Flexible Input Clock Buffer with Divide-by-1, -2, -4
  • SNR = 69.6 dBFS, SFDR = 86 dBc at
    fIN = 70 MHz
  • Ultra-Low Power Consumption:
    • 203 mW/Ch at 160 MSPS
  • Channel Isolation: 105 dB
  • Internal Dither
  • JESD204B Serial Interface:
    • Subclass 0, 1, 2 Compliant up to 3.2 Gbps
    • Supports One Lane per ADC up to 160 MSPS
  • Support for Multi-Chip Synchronization
  • Pin-to-Pin Compatible with 14-Bit Version
  • Package: VQFN-48 (7 mm × 7 mm)

Description

The ADC34J2x are a high-linearity, ultra-low power, dual-channel, 12-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization. The devices support JESD204B interfaces in order to reduce the number of interface lines, thus allowing for high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 12-bit data from each channel. The devices support subclass 1 with interface speeds up to 3.2 Gbps.

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