Highlights
• Ultra Precise Timing for 5G
• Two independent DPLL clock channels plus three additional DPLLs for NCO Hybrid, Split XO and redundant Five output synthesizers
• Any-to-any frequency conversion per channel
• Inputs: up to 10, differential or single-ended
• Outputs: up to 10 differential, up to 20 CMOS
• Output jitter 100 fs RMS typical for 156.25 MHz 12 kHz to 20 MHz
• Core power consumption <0.9W
• Reset-to-clocks <15ms for OUT3 – OUT5
• Physical-layer frequency synchronization
• Processor reset output signal on OUT6N
• Interrupt output signal on OUT6P
• Physical-layer compliance with ITU-T G.8262, G.8262.1, G.813, G.812, Telcordia GR-1244, GR-253
• Hitless reference switching

General Features
• Automatic self-configuration at power-up from internal Flash memory, 7 configurations
• Input-to-output alignment <100 ps
• Numerically controlled oscillator behavior in each DPLL and each synthesizer
• Easy-to-configure design requires no external VCXO or loop filter components
• 5 GPIO pins with many possible behaviors, each REF can be GPI, each OUT can be GPO
• SPI or I2C processor Interface
• 1.8V and 3.3V core VDD voltages
• Easy-to-use evaluation/programming software

The ZL80032 is a feature-rich network synchronization solution with two independent DPLL clock channels plus three additional DPLLs for NCO Hybrid, Split XO and redundant oscillator modes, and five extremely low output jitter synthesizers. This solution is ideal for Synchronous Ethernet (SyncE) central timing applications such as 5G Distributed Units (DU), Centralized Units (CU) and Radio Units (CU).

The ZL80732 is another device in this family which is targeted for 5G SyncE and IEEE1588/PTP timing applications.